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Searched refs:dyn_state (Results 1 – 19 of 19) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Dr600_dpm.c924 ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in r600_parse_extended_power_table()
933 ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in r600_parse_extended_power_table()
936 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries); in r600_parse_extended_power_table()
944 ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in r600_parse_extended_power_table()
947 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries); in r600_parse_extended_power_table()
948 kfree(rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries); in r600_parse_extended_power_table()
956 ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, in r600_parse_extended_power_table()
959 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries); in r600_parse_extended_power_table()
960 kfree(rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries); in r600_parse_extended_power_table()
961 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries); in r600_parse_extended_power_table()
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H A Dbtc_dpm.c1201 return btc_find_valid_clock(&rdev->pm.dpm.dyn_state.valid_mclk_values, in btc_get_valid_mclk()
1208 return btc_find_valid_clock(&rdev->pm.dpm.dyn_state.valid_sclk_values, in btc_get_valid_sclk()
1251 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > rdev->pm.dpm.dyn_state.mclk_sclk_ratio) in btc_adjust_clock_combinations()
1255 (rdev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) / in btc_adjust_clock_combinations()
1256 rdev->pm.dpm.dyn_state.mclk_sclk_ratio); in btc_adjust_clock_combinations()
1258 if ((pl->sclk - pl->mclk) > rdev->pm.dpm.dyn_state.sclk_mclk_delta) in btc_adjust_clock_combinations()
1262 rdev->pm.dpm.dyn_state.sclk_mclk_delta); in btc_adjust_clock_combinations()
1289 if ((*vddc - *vddci) > rdev->pm.dpm.dyn_state.vddc_vddci_delta) { in btc_apply_voltage_delta_rules()
1291 (*vddc - rdev->pm.dpm.dyn_state.vddc_vddci_delta)); in btc_apply_voltage_delta_rules()
1295 if ((*vddci - *vddc) > rdev->pm.dpm.dyn_state.vddc_vddci_delta) { in btc_apply_voltage_delta_rules()
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H A Dsi_dpm.c2100 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; in si_populate_smc_tdp_limits()
2473 &rdev->pm.dpm.dyn_state.cac_leakage_table; in si_get_cac_std_voltage_max_min()
2876 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in si_get_vce_clock_voltage()
2963 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in si_apply_state_adjust_rules()
2965 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in si_apply_state_adjust_rules()
2985 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in si_apply_state_adjust_rules()
2987 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in si_apply_state_adjust_rules()
2989 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in si_apply_state_adjust_rules()
3091 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in si_apply_state_adjust_rules()
3094 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in si_apply_state_adjust_rules()
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H A Dkv_dpm.c398 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid2_to_vid7()
420 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid7_to_vid2()
561 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_program_bootup_state()
663 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in kv_populate_uvd_table()
736 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_populate_vce_table()
797 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; in kv_populate_samu_table()
863 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in kv_populate_acp_table()
922 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_calculate_dfs_bypass_settings()
1247 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in kv_update_uvd_dpm()
1283 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_get_vce_boot_level()
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H A Drv770_dpm.c2261 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; in rv7xx_parse_pplib_clock_info()
2262 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; in rv7xx_parse_pplib_clock_info()
2263 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; in rv7xx_parse_pplib_clock_info()
2264 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; in rv7xx_parse_pplib_clock_info()
H A Dradeon_atombios.c3314 u32 count = rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; in radeon_atom_get_voltage_evv()
3318 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v == in radeon_atom_get_voltage_evv()
3330 cpu_to_le32(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk); in radeon_atom_get_voltage_evv()
H A Dtrinity_dpm.c1462 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in trinity_get_vce_clock_voltage()
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dprocesspptables.c1324 hwmgr->dyn_state.vddc_dependency_on_sclk = NULL; in init_clock_voltage_dependency()
1325 hwmgr->dyn_state.vddci_dependency_on_mclk = NULL; in init_clock_voltage_dependency()
1326 hwmgr->dyn_state.vddc_dependency_on_mclk = NULL; in init_clock_voltage_dependency()
1327 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; in init_clock_voltage_dependency()
1328 hwmgr->dyn_state.mvdd_dependency_on_mclk = NULL; in init_clock_voltage_dependency()
1329 hwmgr->dyn_state.vce_clock_voltage_dependency_table = NULL; in init_clock_voltage_dependency()
1330 hwmgr->dyn_state.uvd_clock_voltage_dependency_table = NULL; in init_clock_voltage_dependency()
1331 hwmgr->dyn_state.samu_clock_voltage_dependency_table = NULL; in init_clock_voltage_dependency()
1332 hwmgr->dyn_state.acp_clock_voltage_dependency_table = NULL; in init_clock_voltage_dependency()
1333 hwmgr->dyn_state.ppm_parameter_table = NULL; in init_clock_voltage_dependency()
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H A Dsmu8_hwmgr.c73 hwmgr->dyn_state.vce_clock_voltage_dependency_table; in smu8_get_eclk_level()
104 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_get_sclk_level()
134 hwmgr->dyn_state.uvd_clock_voltage_dependency_table; in smu8_get_uvd_level()
262 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_construct_max_power_limits_table()
304 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt; in smu8_init_dynamic_state_adjustment_rule_settings()
405 &hwmgr->dyn_state.max_clock_voltage_on_ac); in smu8_get_system_info_data()
444 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_upload_pptable_to_smu()
446 hwmgr->dyn_state.vdd_gfx_dependency_on_sclk; in smu8_upload_pptable_to_smu()
448 hwmgr->dyn_state.acp_clock_voltage_dependency_table; in smu8_upload_pptable_to_smu()
450 hwmgr->dyn_state.uvd_clock_voltage_dependency_table; in smu8_upload_pptable_to_smu()
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H A Dsmu7_hwmgr.c337 hwmgr->dyn_state.mvdd_dependency_on_mclk); in smu7_construct_voltage_tables()
357 hwmgr->dyn_state.vddci_dependency_on_mclk); in smu7_construct_voltage_tables()
382 hwmgr->dyn_state.vddc_dependency_on_mclk); in smu7_construct_voltage_tables()
785 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu7_setup_dpm_tables_v0()
787 hwmgr->dyn_state.vddc_dependency_on_mclk; in smu7_setup_dpm_tables_v0()
789 hwmgr->dyn_state.cac_leakage_table; in smu7_setup_dpm_tables_v0()
839 allowed_vdd_mclk_table = hwmgr->dyn_state.vddci_dependency_on_mclk; in smu7_setup_dpm_tables_v0()
850 allowed_vdd_mclk_table = hwmgr->dyn_state.mvdd_dependency_on_mclk; in smu7_setup_dpm_tables_v0()
1522 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu7_populate_umdpstate_clocks()
2193 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc = in smu7_patch_clock_voltage_limits_with_vddc_leakage()
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H A Dhwmgr.c245 if ((hwmgr->dyn_state.max_clock_voltage_on_dc.sclk == 0) || in hwmgr_hw_init()
246 (hwmgr->dyn_state.max_clock_voltage_on_dc.mclk == 0)) in hwmgr_hw_init()
247 hwmgr->dyn_state.max_clock_voltage_on_dc = in hwmgr_hw_init()
248 hwmgr->dyn_state.max_clock_voltage_on_ac; in hwmgr_hw_init()
H A Dprocess_pptables_v1_0.c582 hwmgr->dyn_state.cac_dtp_table = kzalloc(table_size, GFP_KERNEL); in get_cac_tdp_table()
584 if (NULL == hwmgr->dyn_state.cac_dtp_table) { in get_cac_tdp_table()
848 hwmgr->dyn_state.max_clock_voltage_on_dc.sclk = in init_clock_voltage_dependency()
850 hwmgr->dyn_state.max_clock_voltage_on_dc.mclk = in init_clock_voltage_dependency()
852 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc = in init_clock_voltage_dependency()
854 hwmgr->dyn_state.max_clock_voltage_on_dc.vddci = in init_clock_voltage_dependency()
1217 kfree(hwmgr->dyn_state.cac_dtp_table); in pp_tables_v1_0_uninitialize()
1218 hwmgr->dyn_state.cac_dtp_table = NULL; in pp_tables_v1_0_uninitialize()
H A Dvega10_processpptables.c992 hwmgr->dyn_state.max_clock_voltage_on_dc.sclk = in init_powerplay_extended_tables()
994 hwmgr->dyn_state.max_clock_voltage_on_dc.mclk = in init_powerplay_extended_tables()
996 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc = in init_powerplay_extended_tables()
998 hwmgr->dyn_state.max_clock_voltage_on_dc.vddci = in init_powerplay_extended_tables()
1231 kfree(hwmgr->dyn_state.cac_dtp_table); in vega10_pp_tables_uninitialize()
1232 hwmgr->dyn_state.cac_dtp_table = NULL; in vega10_pp_tables_uninitialize()
H A Dvega10_hwmgr.c803 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = in vega10_set_private_data_based_on_pptable()
805 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = in vega10_set_private_data_based_on_pptable()
807 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = in vega10_set_private_data_based_on_pptable()
809 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = in vega10_set_private_data_based_on_pptable()
817 kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); in vega10_hwmgr_backend_fini()
818 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; in vega10_hwmgr_backend_fini()
3310 &(hwmgr->dyn_state.max_clock_voltage_on_ac) : in vega10_apply_state_adjust_rules()
3311 &(hwmgr->dyn_state.max_clock_voltage_on_dc); in vega10_apply_state_adjust_rules()
3340 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac); in vega10_apply_state_adjust_rules()
H A Dsmu_helper.c529 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt; in phm_initializa_dynamic_state_adjustment_rule_settings()
H A Dsmu7_powertune.c1160 cac_table = hwmgr->dyn_state.cac_dtp_table; in smu7_enable_power_containment()
1250 cac_table = hwmgr->dyn_state.cac_dtp_table; in smu7_power_control_set_level()
/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dci_smumgr.c419 hwmgr->dyn_state.vddc_dependency_on_sclk, clock, in ci_populate_single_graphic_level()
431 hwmgr->dyn_state.vddc_phase_shed_limits_table, in ci_populate_single_graphic_level()
532 tdc_limit = (uint16_t)(hwmgr->dyn_state.cac_dtp_table->usTDC * 256); in ci_populate_tdc_limit()
585 PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.cac_leakage_table, in ci_populate_bapm_vddc_vid_sidd()
587 PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count <= 8, in ci_populate_bapm_vddc_vid_sidd()
589 …PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_… in ci_populate_bapm_vddc_vid_sidd()
592 for (i = 0; (uint32_t) i < hwmgr->dyn_state.cac_leakage_table->count; i++) { in ci_populate_bapm_vddc_vid_sidd()
594 lo_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc1); in ci_populate_bapm_vddc_vid_sidd()
595 hi_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc2); in ci_populate_bapm_vddc_vid_sidd()
596 hi2_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc3); in ci_populate_bapm_vddc_vid_sidd()
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H A Diceland_smumgr.c325 tdc_limit = (uint16_t)(hwmgr->dyn_state.cac_dtp_table->usTDC * 256); in iceland_populate_tdc_limit()
376 struct phm_cac_tdp_table *cac_table = hwmgr->dyn_state.cac_dtp_table; in iceland_populate_bapm_vddc_base_leakage_sidd()
396 PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.cac_leakage_table, in iceland_populate_bapm_vddc_vid_sidd()
398 PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count <= 8, in iceland_populate_bapm_vddc_vid_sidd()
400 …PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_… in iceland_populate_bapm_vddc_vid_sidd()
404 for (i = 0; (uint32_t) i < hwmgr->dyn_state.cac_leakage_table->count; i++) { in iceland_populate_bapm_vddc_vid_sidd()
405 lo_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc1); in iceland_populate_bapm_vddc_vid_sidd()
406 hi_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc2); in iceland_populate_bapm_vddc_vid_sidd()
540 PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.vddc_dependency_on_sclk, in iceland_get_std_voltage_value_sidd()
544 if (NULL == hwmgr->dyn_state.cac_leakage_table) { in iceland_get_std_voltage_value_sidd()
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/linux/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dsi_dpm.c2267 struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table; in si_populate_smc_tdp_limits()
2642 &adev->pm.dpm.dyn_state.cac_leakage_table; in si_get_cac_std_voltage_max_min()
3046 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in si_get_vce_clock_voltage()
3250 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_mclk_values, in btc_get_valid_mclk()
3257 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_sclk_values, in btc_get_valid_sclk()
3310 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio) in btc_adjust_clock_combinations()
3314 (adev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) / in btc_adjust_clock_combinations()
3315 adev->pm.dpm.dyn_state.mclk_sclk_ratio); in btc_adjust_clock_combinations()
3317 if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta) in btc_adjust_clock_combinations()
3321 adev->pm.dpm.dyn_state.sclk_mclk_delta); in btc_adjust_clock_combinations()
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