| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/ |
| H A D | dcn30_hwseq.c | 458 struct dwbc *dwb; in dcn30_update_writeback() local
459 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dcn30_update_writeback()
467 dwb->funcs->update(dwb, &wb_info->dwb_params); in dcn30_update_writeback()
475 struct dwbc *dwb; in dcn30_mmhubbub_warmup() local
481 dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst]; in dcn30_mmhubbub_warmup()
482 if (dwb->dwb_is_efc_transition || dwb->dwb_is_drc) { in dcn30_mmhubbub_warmup()
532 struct dwbc *dwb; in dcn30_enable_writeback() local
535 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dcn30_enable_writeback()
551 dwb->funcs->enable(dwb, &wb_info->dwb_params); in dcn30_enable_writeback()
558 struct dwbc *dwb; in dcn30_disable_writeback() local
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_stream.c | 545 struct dwbc *dwb; in dc_stream_add_writeback() local
566 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
567 dwb->dwb_is_drc = false; in dc_stream_add_writeback()
587 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback() local
589 dwb->otg_inst = stream_status->primary_otg_inst; in dc_stream_add_writeback()
599 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback() local
601 if (dwb->funcs->is_enabled(dwb)) { in dc_stream_add_writeback()
617 struct dwbc *dwb = dc->res_pool->dwbc[dwb_pipe_inst]; in dc_stream_fc_disable_writeback() local
636 if (dwb->funcs->set_fc_enable) in dc_stream_fc_disable_writeback()
637 dwb->funcs->set_fc_enable(dwb, DWB_FRAME_CAPTURE_DISABLE); in dc_stream_fc_disable_writeback()
[all …]
|
| H A D | dc_hw_sequencer.c | 2708 struct dwbc *dwb = params->dwbc_enable_params.dwb; in hwss_dwbc_enable() local
2711 if (dwb->funcs->enable) in hwss_dwbc_enable()
2712 dwb->funcs->enable(dwb, dwb_params); in hwss_dwbc_enable()
2717 struct dwbc *dwb = params->dwbc_disable_params.dwb; in hwss_dwbc_disable() local
2719 if (dwb->funcs->disable) in hwss_dwbc_disable()
2720 dwb->funcs->disable(dwb); in hwss_dwbc_disable()
2725 struct dwbc *dwb = params->dwbc_update_params.dwb; in hwss_dwbc_update() local
2728 if (dwb->funcs->update) in hwss_dwbc_update()
2729 dwb->funcs->update(dwb, dwb_params); in hwss_dwbc_update()
3386 struct dwbc *dwb, in hwss_add_dwbc_update() argument
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/dwb/ |
| H A D | Makefile | 32 AMD_DAL_DWB_DCN30 = $(addprefix $(AMDDALPATH)/dc/dwb/dcn30/,$(DWB_DCN30))
41 AMD_DAL_DWB_DCN35 = $(addprefix $(AMDDALPATH)/dc/dwb/dcn35/,$(DWB_DCN35))
|
| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | Makefile | 25 … clk_mgr dce gpio hwss irq link dsc resource optc dpp hubbub dccg hubp dio dwb hpo mmhubbub mpc op…
|
| H A D | dc.h | 831 bool dwb : 1; /* Display writeback */ member
|
| /linux/drivers/gpu/drm/amd/display/dc/hwss/ |
| H A D | hw_sequencer.h | 506 struct dwbc *dwb; member
511 struct dwbc *dwb; member
515 struct dwbc *dwb; member
1771 struct dwbc *dwb,
1799 struct dwbc *dwb,
1803 struct dwbc *dwb);
|
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 3203 struct dwbc *dwb; in dcn401_program_all_writeback_pipes_in_tree_sequence() local
3238 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dcn401_program_all_writeback_pipes_in_tree_sequence()
3240 if (dwb->funcs->is_enabled(dwb)) { in dcn401_program_all_writeback_pipes_in_tree_sequence()
3261 struct dwbc *dwb; in dcn401_enable_writeback_sequence() local
3267 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dcn401_enable_writeback_sequence()
3271 hwss_add_dwbc_update(seq_state, dwb, &wb_info->dwb_params); in dcn401_enable_writeback_sequence()
3286 hwss_add_dwbc_enable(seq_state, dwb, &wb_info->dwb_params); in dcn401_enable_writeback_sequence()
3294 struct dwbc *dwb; in dcn401_disable_writeback_sequence() local
3300 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dcn401_disable_writeback_sequence()
3304 hwss_add_dwbc_disable(seq_state, dwb); in dcn401_disable_writeback_sequence()
[all …]
|
| /linux/arch/mips/include/asm/octeon/ |
| H A D | cvmx-iob-defs.h | 748 uint64_t dwb:3; member
754 uint64_t dwb:3;
|
| H A D | cvmx-pko-defs.h | 716 uint64_t dwb:9; member
722 uint64_t dwb:9;
|
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| H A D | dcn20_hwseq.c | 2530 struct dwbc *dwb; in dcn20_enable_writeback() local
2536 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dcn20_enable_writeback()
2540 optc = dc->res_pool->timing_generators[dwb->otg_inst]; in dcn20_enable_writeback()
2548 dwb->funcs->enable(dwb, &wb_info->dwb_params); in dcn20_enable_writeback()
2556 struct dwbc *dwb; in dcn20_disable_writeback() local
2560 dwb = dc->res_pool->dwbc[dwb_pipe_inst]; in dcn20_disable_writeback()
2563 dwb->funcs->disable(dwb); in dcn20_disable_writeback()
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn36/ |
| H A D | dcn36_resource.c | 1584 dwbc30, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dwb); in dcn35_dwbc_init()
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| H A D | dcn35_resource.c | 1597 dwbc30, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dwb); in dcn35_dwbc_init()
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
| H A D | dcn351_resource.c | 1577 dwbc30, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dwb); in dcn35_dwbc_init()
|