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Searched refs:dtbclk_mhz (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.c130 .dtbclk_mhz = 625.0,
139 .dtbclk_mhz = 625.0,
148 .dtbclk_mhz = 625.0,
157 .dtbclk_mhz = 625.0,
166 .dtbclk_mhz = 625.0,
374 .dtbclk_mhz = 625.0,
383 .dtbclk_mhz = 625.0,
392 .dtbclk_mhz = 625.0,
401 .dtbclk_mhz = 625.0,
410 .dtbclk_mhz = 625.0,
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c140 .dtbclk_mhz = 1564.0,
2652 if (bw_params->clk_table.entries[i].dtbclk_mhz > max_dtbclk_mhz) in dcn32_patch_dpm_table()
2653 max_dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; in dcn32_patch_dpm_table()
2667 bw_params->clk_table.entries[0].dtbclk_mhz = dcn3_2_soc.clock_limits[0].dtbclk_mhz; in dcn32_patch_dpm_table()
2756 if (max_clk_limit->dtbclk_mhz != 0) in override_max_clk_values()
2757 curr_clk_limit->dtbclk_mhz = max_clk_limit->dtbclk_mhz; in override_max_clk_values()
2798 if (bw_params->clk_table.entries[i].dtbclk_mhz > max_clk_data.dtbclk_mhz) in build_synthetic_soc_states()
2799 max_clk_data.dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; in build_synthetic_soc_states()
2831 if (!max_clk_data.dcfclk_mhz || !max_clk_data.dispclk_mhz || !max_clk_data.dtbclk_mhz) in build_synthetic_soc_states()
2849 entry.dtbclk_mhz = max_clk_data.dtbclk_mhz; in build_synthetic_soc_states()
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/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddml2_translation_helper.c368 p->in_states->state_array[0].dtbclk_mhz = 1564.0; in dml2_init_soc_states()
404 p->in_states->state_array[0].dtbclk_mhz = 1564.0; in dml2_init_soc_states()
441 p->in_states->state_array[0].dtbclk_mhz = 2000; //1564.0; in dml2_init_soc_states()
552 if (dml2->config.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz > 0) in dml2_init_soc_states()
553 p->in_states->state_array[i].dtbclk_mhz = in dml2_init_soc_states()
554 dml2->config.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz; in dml2_init_soc_states()
586 if (p->in_states->state_array[i].dtbclk_mhz > max_dtbclk_mhz) in dml2_init_soc_states()
587 max_dtbclk_mhz = (int)p->in_states->state_array[i].dtbclk_mhz; in dml2_init_soc_states()
596 p->out_states->state_array[i].dtbclk_mhz = max_dtbclk_mhz; in dml2_init_soc_states()
601 p->out_states->state_array[i].dtbclk_mhz = max_dtbclk_mhz; in dml2_init_soc_states()
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H A Ddml2_wrapper_fpu.c421 …_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dtbclk_mhz * 1000; in dml2_validate_and_build_resource()
479 …_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dtbclk_mhz * 1000; in dml2_validate_and_build_resource()
H A Ddisplay_mode_util.c640 dml_print("DML: state_bbox: dtbclk_mhz = %f\n", state->dtbclk_mhz); in dml_print_soc_state_bounding_box()
H A Ddisplay_mode_core_structs.h283 dml_float_t dtbclk_mhz; member
H A Ddisplay_mode_core.c7465 … mode_lib->ms.cache_display_cfg.output.AudioSampleLayout[k]) > mode_lib->ms.state.dtbclk_mhz) { in dml_core_mode_support()
/linux/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/
H A Ddcn42_soc_and_ip_translator.c123 dml_clk_table->dtbclk.clk_values_khz[i] = dc_clk_table->entries[i].dtbclk_mhz * 1000; in dcn42_convert_dc_clock_table_to_soc_bb_clock_table()
/linux/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_mode_structs.h169 double dtbclk_mhz; member
H A Ddisplay_mode_vba.c406 mode_lib->vba.DTBCLKPerState[i] = soc->clock_limits[i].dtbclk_mhz; in fetch_socbb_params()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c2390 low_pstate_lvl.dtbclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dtbclk_mhz; in construct_low_pstate_lvl()
2444 s[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; in dcn21_update_bw_bounding_box_fpu()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/
H A Ddcn42_clk_mgr.c1002 clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz = 600; /* Fixed on platform */ in dcn42_get_smu_clocks()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c81 clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000; in dcn401_initialize_min_clocks()