1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */ 2 /* 3 * Copyright 2016-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef F32_MES_PM4_PACKETS_H 26 #define F32_MES_PM4_PACKETS_H 27 28 #ifndef PM4_MES_HEADER_DEFINED 29 #define PM4_MES_HEADER_DEFINED 30 union PM4_MES_TYPE_3_HEADER { 31 struct { 32 uint32_t reserved1 : 8; /* < reserved */ 33 uint32_t opcode : 8; /* < IT opcode */ 34 uint32_t count : 14;/* < number of DWORDs - 1 in the 35 * information body. 36 */ 37 uint32_t type : 2; /* < packet identifier. 38 * It should be 3 for type 3 packets 39 */ 40 }; 41 uint32_t u32All; 42 }; 43 #endif /* PM4_MES_HEADER_DEFINED */ 44 45 /*--------------------MES_SET_RESOURCES--------------------*/ 46 47 #ifndef PM4_MES_SET_RESOURCES_DEFINED 48 #define PM4_MES_SET_RESOURCES_DEFINED 49 enum mes_set_resources_queue_type_enum { 50 queue_type__mes_set_resources__kernel_interface_queue_kiq = 0, 51 queue_type__mes_set_resources__hsa_interface_queue_hiq = 1, 52 queue_type__mes_set_resources__hsa_debug_interface_queue = 4 53 }; 54 55 56 struct pm4_mes_set_resources { 57 union { 58 union PM4_MES_TYPE_3_HEADER header; /* header */ 59 uint32_t ordinal1; 60 }; 61 62 union { 63 struct { 64 uint32_t vmid_mask:16; 65 uint32_t unmap_latency:8; 66 uint32_t reserved1:5; 67 enum mes_set_resources_queue_type_enum queue_type:3; 68 } bitfields2; 69 uint32_t ordinal2; 70 }; 71 72 uint32_t queue_mask_lo; 73 uint32_t queue_mask_hi; 74 uint32_t gws_mask_lo; 75 uint32_t gws_mask_hi; 76 77 union { 78 struct { 79 uint32_t oac_mask:16; 80 uint32_t reserved2:16; 81 } bitfields7; 82 uint32_t ordinal7; 83 }; 84 85 union { 86 struct { 87 uint32_t gds_heap_base:10; 88 uint32_t reserved3:1; 89 uint32_t gds_heap_size:10; 90 uint32_t reserved4:11; 91 } bitfields8; 92 uint32_t ordinal8; 93 }; 94 95 }; 96 #endif 97 98 /*--------------------MES_RUN_LIST--------------------*/ 99 100 #ifndef PM4_MES_RUN_LIST_DEFINED 101 #define PM4_MES_RUN_LIST_DEFINED 102 103 struct pm4_mes_runlist { 104 union { 105 union PM4_MES_TYPE_3_HEADER header; /* header */ 106 uint32_t ordinal1; 107 }; 108 109 union { 110 struct { 111 uint32_t reserved1:2; 112 uint32_t ib_base_lo:30; 113 } bitfields2; 114 uint32_t ordinal2; 115 }; 116 117 uint32_t ib_base_hi; 118 119 union { 120 struct { 121 uint32_t ib_size:20; 122 uint32_t chain:1; 123 uint32_t offload_polling:1; 124 uint32_t chained_runlist_idle_disable:1; 125 uint32_t valid:1; 126 uint32_t process_cnt:4; 127 uint32_t reserved3:4; 128 } bitfields4; 129 uint32_t ordinal4; 130 }; 131 132 }; 133 #endif 134 135 /*--------------------MES_MAP_PROCESS--------------------*/ 136 137 #ifndef PM4_MES_MAP_PROCESS_DEFINED 138 #define PM4_MES_MAP_PROCESS_DEFINED 139 140 struct pm4_mes_map_process { 141 union { 142 union PM4_MES_TYPE_3_HEADER header; /* header */ 143 uint32_t ordinal1; 144 }; 145 146 union { 147 struct { 148 uint32_t pasid:16; /* 0 - 15 */ 149 uint32_t reserved1:1; /* 16 */ 150 uint32_t exec_cleaner_shader:1; /* 17 */ 151 uint32_t debug_vmid:4; 152 uint32_t new_debug:1; 153 uint32_t reserved2:1; 154 uint32_t diq_enable:1; 155 uint32_t process_quantum:7; 156 } bitfields2; 157 uint32_t ordinal2; 158 }; 159 160 uint32_t vm_context_page_table_base_addr_lo32; 161 162 uint32_t vm_context_page_table_base_addr_hi32; 163 164 uint32_t sh_mem_bases; 165 166 uint32_t sh_mem_config; 167 168 uint32_t sq_shader_tba_lo; 169 170 uint32_t sq_shader_tba_hi; 171 172 uint32_t sq_shader_tma_lo; 173 174 uint32_t sq_shader_tma_hi; 175 176 uint32_t reserved6; 177 178 uint32_t gds_addr_lo; 179 180 uint32_t gds_addr_hi; 181 182 union { 183 struct { 184 uint32_t num_gws:7; 185 uint32_t sdma_enable:1; 186 uint32_t num_oac:4; 187 uint32_t gds_size_hi:4; 188 uint32_t gds_size:6; 189 uint32_t num_queues:10; 190 } bitfields14; 191 uint32_t ordinal14; 192 }; 193 194 uint32_t completion_signal_lo; 195 196 uint32_t completion_signal_hi; 197 198 }; 199 200 #endif 201 202 /*--------------------MES_MAP_PROCESS_VM--------------------*/ 203 204 #ifndef PM4_MES_MAP_PROCESS_VM_DEFINED 205 #define PM4_MES_MAP_PROCESS_VM_DEFINED 206 207 struct PM4_MES_MAP_PROCESS_VM { 208 union { 209 union PM4_MES_TYPE_3_HEADER header; /* header */ 210 uint32_t ordinal1; 211 }; 212 213 uint32_t reserved1; 214 215 uint32_t vm_context_cntl; 216 217 uint32_t reserved2; 218 219 uint32_t vm_context_page_table_end_addr_lo32; 220 221 uint32_t vm_context_page_table_end_addr_hi32; 222 223 uint32_t vm_context_page_table_start_addr_lo32; 224 225 uint32_t vm_context_page_table_start_addr_hi32; 226 227 uint32_t reserved3; 228 229 uint32_t reserved4; 230 231 uint32_t reserved5; 232 233 uint32_t reserved6; 234 235 uint32_t reserved7; 236 237 uint32_t reserved8; 238 239 uint32_t completion_signal_lo32; 240 241 uint32_t completion_signal_hi32; 242 243 }; 244 #endif 245 246 /*--------------------MES_MAP_QUEUES--------------------*/ 247 248 #ifndef PM4_MES_MAP_QUEUES_VI_DEFINED 249 #define PM4_MES_MAP_QUEUES_VI_DEFINED 250 enum mes_map_queues_queue_sel_enum { 251 queue_sel__mes_map_queues__map_to_specified_queue_slots_vi = 0, 252 queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi = 1 253 }; 254 255 enum mes_map_queues_queue_type_enum { 256 queue_type__mes_map_queues__normal_compute_vi = 0, 257 queue_type__mes_map_queues__debug_interface_queue_vi = 1, 258 queue_type__mes_map_queues__normal_latency_static_queue_vi = 2, 259 queue_type__mes_map_queues__low_latency_static_queue_vi = 3 260 }; 261 262 enum mes_map_queues_engine_sel_enum { 263 engine_sel__mes_map_queues__compute_vi = 0, 264 engine_sel__mes_map_queues__sdma0_vi = 2, 265 engine_sel__mes_map_queues__sdma1_vi = 3 266 }; 267 268 enum mes_map_queues_extended_engine_sel_enum { 269 extended_engine_sel__mes_map_queues__legacy_engine_sel = 0, 270 extended_engine_sel__mes_map_queues__sdma0_to_7_sel = 1, 271 extended_engine_sel__mes_map_queues__sdma8_to_15_sel = 2 272 }; 273 274 struct pm4_mes_map_queues { 275 union { 276 union PM4_MES_TYPE_3_HEADER header; /* header */ 277 uint32_t ordinal1; 278 }; 279 280 union { 281 struct { 282 uint32_t reserved1:2; 283 enum mes_map_queues_extended_engine_sel_enum extended_engine_sel:2; 284 enum mes_map_queues_queue_sel_enum queue_sel:2; 285 uint32_t reserved5:6; 286 uint32_t gws_control_queue:1; 287 uint32_t reserved2:8; 288 enum mes_map_queues_queue_type_enum queue_type:3; 289 uint32_t reserved3:2; 290 enum mes_map_queues_engine_sel_enum engine_sel:3; 291 uint32_t num_queues:3; 292 } bitfields2; 293 uint32_t ordinal2; 294 }; 295 296 union { 297 struct { 298 uint32_t reserved3:1; 299 uint32_t check_disable:1; 300 uint32_t doorbell_offset:26; 301 uint32_t reserved4:4; 302 } bitfields3; 303 uint32_t ordinal3; 304 }; 305 306 uint32_t mqd_addr_lo; 307 uint32_t mqd_addr_hi; 308 uint32_t wptr_addr_lo; 309 uint32_t wptr_addr_hi; 310 }; 311 #endif 312 313 /*--------------------MES_QUERY_STATUS--------------------*/ 314 315 #ifndef PM4_MES_QUERY_STATUS_DEFINED 316 #define PM4_MES_QUERY_STATUS_DEFINED 317 enum mes_query_status_interrupt_sel_enum { 318 interrupt_sel__mes_query_status__completion_status = 0, 319 interrupt_sel__mes_query_status__process_status = 1, 320 interrupt_sel__mes_query_status__queue_status = 2 321 }; 322 323 enum mes_query_status_command_enum { 324 command__mes_query_status__interrupt_only = 0, 325 command__mes_query_status__fence_only_immediate = 1, 326 command__mes_query_status__fence_only_after_write_ack = 2, 327 command__mes_query_status__fence_wait_for_write_ack_send_interrupt = 3 328 }; 329 330 enum mes_query_status_engine_sel_enum { 331 engine_sel__mes_query_status__compute = 0, 332 engine_sel__mes_query_status__sdma0_queue = 2, 333 engine_sel__mes_query_status__sdma1_queue = 3 334 }; 335 336 struct pm4_mes_query_status { 337 union { 338 union PM4_MES_TYPE_3_HEADER header; /* header */ 339 uint32_t ordinal1; 340 }; 341 342 union { 343 struct { 344 uint32_t context_id:28; 345 enum mes_query_status_interrupt_sel_enum interrupt_sel:2; 346 enum mes_query_status_command_enum command:2; 347 } bitfields2; 348 uint32_t ordinal2; 349 }; 350 351 union { 352 struct { 353 uint32_t pasid:16; 354 uint32_t reserved1:16; 355 } bitfields3a; 356 struct { 357 uint32_t reserved2:2; 358 uint32_t doorbell_offset:26; 359 enum mes_query_status_engine_sel_enum engine_sel:3; 360 uint32_t reserved3:1; 361 } bitfields3b; 362 uint32_t ordinal3; 363 }; 364 365 uint32_t addr_lo; 366 uint32_t addr_hi; 367 uint32_t data_lo; 368 uint32_t data_hi; 369 }; 370 #endif 371 372 /*--------------------MES_UNMAP_QUEUES--------------------*/ 373 374 #ifndef PM4_MES_UNMAP_QUEUES_DEFINED 375 #define PM4_MES_UNMAP_QUEUES_DEFINED 376 enum mes_unmap_queues_action_enum { 377 action__mes_unmap_queues__preempt_queues = 0, 378 action__mes_unmap_queues__reset_queues = 1, 379 action__mes_unmap_queues__disable_process_queues = 2, 380 action__mes_unmap_queues__reserved = 3 381 }; 382 383 enum mes_unmap_queues_queue_sel_enum { 384 queue_sel__mes_unmap_queues__perform_request_on_specified_queues = 0, 385 queue_sel__mes_unmap_queues__perform_request_on_pasid_queues = 1, 386 queue_sel__mes_unmap_queues__unmap_all_queues = 2, 387 queue_sel__mes_unmap_queues__unmap_all_non_static_queues = 3 388 }; 389 390 enum mes_unmap_queues_engine_sel_enum { 391 engine_sel__mes_unmap_queues__compute = 0, 392 engine_sel__mes_unmap_queues__sdma0 = 2, 393 engine_sel__mes_unmap_queues__sdmal = 3 394 }; 395 396 enum mes_unmap_queues_extended_engine_sel_enum { 397 extended_engine_sel__mes_unmap_queues__legacy_engine_sel = 0, 398 extended_engine_sel__mes_unmap_queues__sdma0_to_7_sel = 1 399 }; 400 401 struct pm4_mes_unmap_queues { 402 union { 403 union PM4_MES_TYPE_3_HEADER header; /* header */ 404 uint32_t ordinal1; 405 }; 406 407 union { 408 struct { 409 enum mes_unmap_queues_action_enum action:2; 410 enum mes_unmap_queues_extended_engine_sel_enum extended_engine_sel:2; 411 enum mes_unmap_queues_queue_sel_enum queue_sel:2; 412 uint32_t reserved2:20; 413 enum mes_unmap_queues_engine_sel_enum engine_sel:3; 414 uint32_t num_queues:3; 415 } bitfields2; 416 uint32_t ordinal2; 417 }; 418 419 union { 420 struct { 421 uint32_t pasid:16; 422 uint32_t reserved3:16; 423 } bitfields3a; 424 struct { 425 uint32_t reserved4:2; 426 uint32_t doorbell_offset0:26; 427 int32_t reserved5:4; 428 } bitfields3b; 429 uint32_t ordinal3; 430 }; 431 432 union { 433 struct { 434 uint32_t reserved6:2; 435 uint32_t doorbell_offset1:26; 436 uint32_t reserved7:4; 437 } bitfields4; 438 uint32_t ordinal4; 439 }; 440 441 union { 442 struct { 443 uint32_t reserved8:2; 444 uint32_t doorbell_offset2:26; 445 uint32_t reserved9:4; 446 } bitfields5; 447 uint32_t ordinal5; 448 }; 449 450 union { 451 struct { 452 uint32_t reserved10:2; 453 uint32_t doorbell_offset3:26; 454 uint32_t reserved11:4; 455 } bitfields6; 456 uint32_t ordinal6; 457 }; 458 }; 459 #endif 460 461 #ifndef PM4_MEC_RELEASE_MEM_DEFINED 462 #define PM4_MEC_RELEASE_MEM_DEFINED 463 464 enum mec_release_mem_event_index_enum { 465 event_index__mec_release_mem__end_of_pipe = 5, 466 event_index__mec_release_mem__shader_done = 6 467 }; 468 469 enum mec_release_mem_cache_policy_enum { 470 cache_policy__mec_release_mem__lru = 0, 471 cache_policy__mec_release_mem__stream = 1 472 }; 473 474 enum mec_release_mem_pq_exe_status_enum { 475 pq_exe_status__mec_release_mem__default = 0, 476 pq_exe_status__mec_release_mem__phase_update = 1 477 }; 478 479 enum mec_release_mem_dst_sel_enum { 480 dst_sel__mec_release_mem__memory_controller = 0, 481 dst_sel__mec_release_mem__tc_l2 = 1, 482 dst_sel__mec_release_mem__queue_write_pointer_register = 2, 483 dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit = 3 484 }; 485 486 enum mec_release_mem_int_sel_enum { 487 int_sel__mec_release_mem__none = 0, 488 int_sel__mec_release_mem__send_interrupt_only = 1, 489 int_sel__mec_release_mem__send_interrupt_after_write_confirm = 2, 490 int_sel__mec_release_mem__send_data_after_write_confirm = 3, 491 int_sel__mec_release_mem__unconditionally_send_int_ctxid = 4, 492 int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare = 5, 493 int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare = 6 494 }; 495 496 enum mec_release_mem_data_sel_enum { 497 data_sel__mec_release_mem__none = 0, 498 data_sel__mec_release_mem__send_32_bit_low = 1, 499 data_sel__mec_release_mem__send_64_bit_data = 2, 500 data_sel__mec_release_mem__send_gpu_clock_counter = 3, 501 data_sel__mec_release_mem__send_cp_perfcounter_hi_lo = 4, 502 data_sel__mec_release_mem__store_gds_data_to_memory = 5 503 }; 504 505 struct pm4_mec_release_mem { 506 union { 507 union PM4_MES_TYPE_3_HEADER header; /*header */ 508 unsigned int ordinal1; 509 }; 510 511 union { 512 struct { 513 unsigned int event_type:6; 514 unsigned int reserved1:2; 515 enum mec_release_mem_event_index_enum event_index:4; 516 unsigned int tcl1_vol_action_ena:1; 517 unsigned int tc_vol_action_ena:1; 518 unsigned int reserved2:1; 519 unsigned int tc_wb_action_ena:1; 520 unsigned int tcl1_action_ena:1; 521 unsigned int tc_action_ena:1; 522 uint32_t reserved3:1; 523 uint32_t tc_nc_action_ena:1; 524 uint32_t tc_wc_action_ena:1; 525 uint32_t tc_md_action_ena:1; 526 uint32_t reserved4:3; 527 enum mec_release_mem_cache_policy_enum cache_policy:2; 528 uint32_t reserved5:2; 529 enum mec_release_mem_pq_exe_status_enum pq_exe_status:1; 530 uint32_t reserved6:2; 531 } bitfields2; 532 unsigned int ordinal2; 533 }; 534 535 union { 536 struct { 537 uint32_t reserved7:16; 538 enum mec_release_mem_dst_sel_enum dst_sel:2; 539 uint32_t reserved8:6; 540 enum mec_release_mem_int_sel_enum int_sel:3; 541 uint32_t reserved9:2; 542 enum mec_release_mem_data_sel_enum data_sel:3; 543 } bitfields3; 544 unsigned int ordinal3; 545 }; 546 547 union { 548 struct { 549 uint32_t reserved10:2; 550 unsigned int address_lo_32b:30; 551 } bitfields4; 552 struct { 553 uint32_t reserved11:3; 554 uint32_t address_lo_64b:29; 555 } bitfields4b; 556 uint32_t reserved12; 557 unsigned int ordinal4; 558 }; 559 560 union { 561 uint32_t address_hi; 562 uint32_t reserved13; 563 uint32_t ordinal5; 564 }; 565 566 union { 567 uint32_t data_lo; 568 uint32_t cmp_data_lo; 569 struct { 570 uint32_t dw_offset:16; 571 uint32_t num_dwords:16; 572 } bitfields6c; 573 uint32_t reserved14; 574 uint32_t ordinal6; 575 }; 576 577 union { 578 uint32_t data_hi; 579 uint32_t cmp_data_hi; 580 uint32_t reserved15; 581 uint32_t reserved16; 582 uint32_t ordinal7; 583 }; 584 585 uint32_t int_ctxid; 586 587 }; 588 589 #endif 590 591 #ifndef PM4_MEC_WRITE_DATA_DEFINED 592 #define PM4_MEC_WRITE_DATA_DEFINED 593 594 enum WRITE_DATA_dst_sel_enum { 595 dst_sel___write_data__mem_mapped_register = 0, 596 dst_sel___write_data__tc_l2 = 2, 597 dst_sel___write_data__gds = 3, 598 dst_sel___write_data__memory = 5, 599 dst_sel___write_data__memory_mapped_adc_persistent_state = 6, 600 }; 601 602 enum WRITE_DATA_addr_incr_enum { 603 addr_incr___write_data__increment_address = 0, 604 addr_incr___write_data__do_not_increment_address = 1 605 }; 606 607 enum WRITE_DATA_wr_confirm_enum { 608 wr_confirm___write_data__do_not_wait_for_write_confirmation = 0, 609 wr_confirm___write_data__wait_for_write_confirmation = 1 610 }; 611 612 enum WRITE_DATA_cache_policy_enum { 613 cache_policy___write_data__lru = 0, 614 cache_policy___write_data__stream = 1 615 }; 616 617 618 struct pm4_mec_write_data_mmio { 619 union { 620 union PM4_MES_TYPE_3_HEADER header; /*header */ 621 unsigned int ordinal1; 622 }; 623 624 union { 625 struct { 626 unsigned int reserved1:8; 627 unsigned int dst_sel:4; 628 unsigned int reserved2:4; 629 unsigned int addr_incr:1; 630 unsigned int reserved3:2; 631 unsigned int resume_vf:1; 632 unsigned int wr_confirm:1; 633 unsigned int reserved4:4; 634 unsigned int cache_policy:2; 635 unsigned int reserved5:5; 636 } bitfields2; 637 unsigned int ordinal2; 638 }; 639 640 union { 641 struct { 642 unsigned int dst_mmreg_addr:18; 643 unsigned int reserved6:14; 644 } bitfields3; 645 unsigned int ordinal3; 646 }; 647 648 uint32_t reserved7; 649 650 uint32_t data; 651 652 }; 653 654 #endif 655 656 enum { 657 CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014 658 }; 659 #endif 660 661