Searched refs:dss1 (Results 1 – 3 of 3) sorted by relevance
2514 u32 dss1; in intel_ddi_mso_get_config() local2519 dss1 = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); in intel_ddi_mso_get_config()2521 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; in intel_ddi_mso_get_config()2530 switch (dss1 & SPLITTER_CONFIGURATION_MASK) { in intel_ddi_mso_get_config()2533 "Invalid splitter configuration, dss1=0x%08x\n", dss1); in intel_ddi_mso_get_config()2543 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); in intel_ddi_mso_get_config()2551 u32 dss1 = 0; in intel_ddi_mso_configure() local2557 dss1 |= SPLITTER_ENABLE; in intel_ddi_mso_configure()2558 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); in intel_ddi_mso_configure()2560 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; in intel_ddi_mso_configure()[all …]
192 dss1_alwon_fck: clock-dss1-alwon-fck-3430es2@0 {
180 static bool ff_dss_match_fh(const struct nfs4_ff_layout_ds_stripe *dss1, in ff_dss_match_fh() argument185 if (dss1->fh_versions_cnt != dss2->fh_versions_cnt) in ff_dss_match_fh()188 for (i = 0; i < dss1->fh_versions_cnt; i++) { in ff_dss_match_fh()191 if (nfs_compare_fh(&dss1->fh_versions[i], in ff_dss_match_fh()