Searched refs:dspcntr (Results 1 – 3 of 3) sorted by relevance
108 u32 dpll = 0, fp = 0, dspcntr, pipeconf; in psb_intel_crtc_mode_set() local201 dspcntr = DISPPLANE_GAMMA_ENABLE; in psb_intel_crtc_mode_set()204 dspcntr |= DISPPLANE_SEL_PIPE_A; in psb_intel_crtc_mode_set()206 dspcntr |= DISPPLANE_SEL_PIPE_B; in psb_intel_crtc_mode_set()208 dspcntr |= DISPLAY_PLANE_ENABLE; in psb_intel_crtc_mode_set()293 REG_WRITE(map->cntr, dspcntr); in psb_intel_crtc_mode_set()
69 u32 dspcntr; in gma_pipe_set_base() local93 dspcntr = REG_READ(map->cntr); in gma_pipe_set_base()94 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; in gma_pipe_set_base()98 dspcntr |= DISPPLANE_8BPP; in gma_pipe_set_base()102 dspcntr |= DISPPLANE_15_16BPP; in gma_pipe_set_base()104 dspcntr |= DISPPLANE_16BPP; in gma_pipe_set_base()108 dspcntr |= DISPPLANE_32BPP_NO_ALPHA; in gma_pipe_set_base()115 REG_WRITE(map->cntr, dspcntr); in gma_pipe_set_base()
585 u32 dpll = 0, dspcntr, pipeconf; in cdv_intel_crtc_mode_set() local713 dspcntr = DISPPLANE_GAMMA_ENABLE; in cdv_intel_crtc_mode_set()716 dspcntr |= DISPPLANE_SEL_PIPE_A; in cdv_intel_crtc_mode_set()718 dspcntr |= DISPPLANE_SEL_PIPE_B; in cdv_intel_crtc_mode_set()720 dspcntr |= DISPLAY_PLANE_ENABLE; in cdv_intel_crtc_mode_set()809 REG_WRITE(map->cntr, dspcntr); in cdv_intel_crtc_mode_set()