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Searched refs:dsi_ctx (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/gpu/drm/panel/
H A Dpanel-novatek-nt35532.c57 struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; in rimob_panel_on() local
59 mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xff, 0x01); in rimob_panel_on()
60 mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6e, 0x80); in rimob_panel_on()
61 mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x68, 0x13); in rimob_panel_on()
62 mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfb, 0x01); in rimob_panel_on()
64 mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xff, 0x02); in rimob_panel_on()
65 mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfb, 0x01); in rimob_panel_on()
67 mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xff, 0x05); in rimob_panel_on()
68 mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfb, 0x01); in rimob_panel_on()
69 mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd7, 0x31); in rimob_panel_on()
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H A Dpanel-himax-hx83121a.c55 int (*init_sequence_dsc)(struct mipi_dsi_multi_context *dsi_ctx);
56 int (*init_sequence)(struct mipi_dsi_multi_context *dsi_ctx);
91 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; in himax_prepare() local
103 ret = ctx->desc->init_sequence_dsc(&dsi_ctx); in himax_prepare()
105 ret = ctx->desc->init_sequence(&dsi_ctx); in himax_prepare()
118 mipi_dsi_picture_parameter_set_multi(&dsi_ctx, &pps); in himax_prepare()
119 mipi_dsi_compression_mode_multi(&dsi_ctx, true); in himax_prepare()
125 static int himax_off(struct mipi_dsi_multi_context *dsi_ctx) in himax_off() argument
127 mipi_dsi_dcs_enter_sleep_mode_multi(dsi_ctx); in himax_off()
128 mipi_dsi_msleep(dsi_ctx, 120); in himax_off()
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H A Dpanel-visionox-rm692e5.c56 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; in visionox_rm692e5_on() local
60 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfe, 0x40); in visionox_rm692e5_on()
61 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xbd, 0x07); in visionox_rm692e5_on()
62 mipi_dsi_usleep_range(&dsi_ctx, 17000, 18000); in visionox_rm692e5_on()
63 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfe, 0xd2); in visionox_rm692e5_on()
64 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x11); in visionox_rm692e5_on()
65 mipi_dsi_dcs_set_display_brightness_multi(&dsi_ctx, 0x00ab); in visionox_rm692e5_on()
66 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x30); in visionox_rm692e5_on()
67 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x09); in visionox_rm692e5_on()
68 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x60); in visionox_rm692e5_on()
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H A Dpanel-sitronix-st7703.c73 void (*init_sequence)(struct mipi_dsi_multi_context *dsi_ctx);
81 static void jh057n_init_sequence(struct mipi_dsi_multi_context *dsi_ctx) in jh057n_init_sequence() argument
88 mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETEXTC, in jh057n_init_sequence()
90 mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETRGBIF, in jh057n_init_sequence()
93 mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETSCR, in jh057n_init_sequence()
96 mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETVDC, 0x4E); in jh057n_init_sequence()
97 mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETPANEL, 0x0B); in jh057n_init_sequence()
98 mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETCYC, 0x80); in jh057n_init_sequence()
99 mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETDISP, 0xF0, 0x12, 0x30); in jh057n_init_sequence()
100 mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETEQ, in jh057n_init_sequence()
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H A Dpanel-himax-hx83112b.c70 struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; in hx83112b_on() local
72 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_SETEXTC, 0x83, 0x11, 0x2b); in hx83112b_on()
73 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_SETBANK, 0x01); in hx83112b_on()
74 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_SETDISMO, 0x08, 0x70); in hx83112b_on()
75 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_SETBANK, 0x03); in hx83112b_on()
76 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_SETDISP, 0x04, 0x38, 0x08, 0x70); in hx83112b_on()
77 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_SETBANK, 0x00); in hx83112b_on()
78 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_SETPOWER1, in hx83112b_on()
81 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_SETPOWER2, 0x2d, 0x2d); in hx83112b_on()
82 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_SETDISP, in hx83112b_on()
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H A Dpanel-himax-hx8394.c84 void (*init_sequence)(struct mipi_dsi_multi_context *dsi_ctx);
92 static void hsd060bhw4_init_sequence(struct mipi_dsi_multi_context *dsi_ctx) in hsd060bhw4_init_sequence() argument
95 mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETEXTC, in hsd060bhw4_init_sequence()
99 mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETPOWER, in hsd060bhw4_init_sequence()
103 mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETMIPI, in hsd060bhw4_init_sequence()
107 mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETDISP, in hsd060bhw4_init_sequence()
111 mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETCYC, in hsd060bhw4_init_sequence()
117 mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGIP0, in hsd060bhw4_init_sequence()
124 mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGIP1, in hsd060bhw4_init_sequence()
132 mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGIP2, in hsd060bhw4_init_sequence()
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H A Dpanel-orisetech-otm8009a.c120 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; in otm8009a_init_sequence() local
123 dcs_write_cmd_at(&dsi_ctx, MCS_CMD2_ENA1, 0x80, 0x09, 0x01); in otm8009a_init_sequence()
126 dcs_write_cmd_at(&dsi_ctx, MCS_CMD2_ENA2, 0x80, 0x09); in otm8009a_init_sequence()
128 dcs_write_cmd_at(&dsi_ctx, MCS_SD_PCH_CTRL, 0x30); in otm8009a_init_sequence()
129 mipi_dsi_msleep(&dsi_ctx, 10); in otm8009a_init_sequence()
131 dcs_write_cmd_at(&dsi_ctx, MCS_NO_DOC1, 0x40); in otm8009a_init_sequence()
132 mipi_dsi_msleep(&dsi_ctx, 10); in otm8009a_init_sequence()
134 dcs_write_cmd_at(&dsi_ctx, MCS_PWR_CTRL4 + 1, 0xA9); in otm8009a_init_sequence()
135 dcs_write_cmd_at(&dsi_ctx, MCS_PWR_CTRL2 + 1, 0x34); in otm8009a_init_sequence()
136 dcs_write_cmd_at(&dsi_ctx, MCS_P_DRV_M, 0x50); in otm8009a_init_sequence()
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H A Dpanel-novatek-nt37801.c50 #define novatek_nt37801_switch_page(dsi_ctx, page) \ argument
51 mipi_dsi_dcs_write_seq_multi((dsi_ctx), NT37801_DCS_SWITCH_PAGE, \
54 static void novatek_nt37801_on(struct mipi_dsi_multi_context *dsi_ctx) in novatek_nt37801_on() argument
56 dsi_ctx->dsi->mode_flags |= MIPI_DSI_MODE_LPM; in novatek_nt37801_on()
58 novatek_nt37801_switch_page(dsi_ctx, 0x01); in novatek_nt37801_on()
59 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x6f, 0x01); in novatek_nt37801_on()
60 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xc5, 0x0b, 0x0b, 0x0b); in novatek_nt37801_on()
61 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xff, 0xaa, 0x55, 0xa5, 0x80); in novatek_nt37801_on()
62 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x6f, 0x02); in novatek_nt37801_on()
63 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xf5, 0x10); in novatek_nt37801_on()
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H A Dpanel-novatek-nt35560.c151 struct mipi_dsi_multi_context dsi_ctx = { in nt35560_set_brightness() local
161 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, in nt35560_set_brightness()
164 return dsi_ctx.accum_err; in nt35560_set_brightness()
185 mipi_dsi_dcs_write_var_seq_multi(&dsi_ctx, in nt35560_set_brightness()
189 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf3, 0xaa); in nt35560_set_brightness()
190 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x01); in nt35560_set_brightness()
191 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x01); in nt35560_set_brightness()
193 mipi_dsi_dcs_write_var_seq_multi(&dsi_ctx, 0x22, pwm_div); in nt35560_set_brightness()
195 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0xaa); in nt35560_set_brightness()
198 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_CONTROL_DISPLAY, in nt35560_set_brightness()
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H A Dpanel-boe-td4320.c48 struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; in boe_td4320_on() local
52 mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb0, 0x04); in boe_td4320_on()
53 mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd6, 0x00); in boe_td4320_on()
54 mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb8, in boe_td4320_on()
57 mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb9, in boe_td4320_on()
60 mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xba, in boe_td4320_on()
63 mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf9, in boe_td4320_on()
65 mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xce, in boe_td4320_on()
72 mipi_dsi_dcs_set_display_brightness_multi(&dsi_ctx, 0x00b8); in boe_td4320_on()
73 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_CONTROL_DISPLAY, in boe_td4320_on()
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H A Dpanel-samsung-s6e88a0-ams427ap24.c456 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; in s6e88a0_ams427ap24_set_brightness() local
509 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0x5a, 0x5a); // level 1 key on in s6e88a0_ams427ap24_set_brightness()
510 mipi_dsi_dcs_write_buffer_multi(&dsi_ctx, b2, ARRAY_SIZE(b2)); // set aid in s6e88a0_ams427ap24_set_brightness()
511 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x00); // acl off in s6e88a0_ams427ap24_set_brightness()
512 mipi_dsi_dcs_write_buffer_multi(&dsi_ctx, b6, ARRAY_SIZE(b6)); // set elvss in s6e88a0_ams427ap24_set_brightness()
513 mipi_dsi_dcs_write_buffer_multi(&dsi_ctx, ca, ARRAY_SIZE(ca)); // set gamma in s6e88a0_ams427ap24_set_brightness()
514 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf7, 0x03); // gamma update in s6e88a0_ams427ap24_set_brightness()
515 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0xa5, 0xa5); // level 1 key off in s6e88a0_ams427ap24_set_brightness()
517 return dsi_ctx.accum_err; in s6e88a0_ams427ap24_set_brightness()
533 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; in s6e88a0_ams427ap24_on() local
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H A Dpanel-samsung-s6e8fc0-m1906f9.c59 struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; in s6e8fc0_m1906f9_on() local
61 s6e8fc0_test_key_on_lvl3(&dsi_ctx); in s6e8fc0_m1906f9_on()
63 mipi_dsi_dcs_set_display_brightness_multi(&dsi_ctx, 0x0000); in s6e8fc0_m1906f9_on()
64 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_CONTROL_DISPLAY, in s6e8fc0_m1906f9_on()
66 mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); in s6e8fc0_m1906f9_on()
67 mipi_dsi_msleep(&dsi_ctx, 50); in s6e8fc0_m1906f9_on()
68 mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); in s6e8fc0_m1906f9_on()
70 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb0, 0x04, 0xed); in s6e8fc0_m1906f9_on()
71 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xed, in s6e8fc0_m1906f9_on()
74 s6e8fc0_test_key_off_lvl3(&dsi_ctx); in s6e8fc0_m1906f9_on()
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H A Dpanel-sony-td4353-jdi.c50 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; in sony_td4353_jdi_on() local
54 mipi_dsi_dcs_set_column_address_multi(&dsi_ctx, 0x0000, 1080 - 1); in sony_td4353_jdi_on()
55 mipi_dsi_dcs_set_page_address_multi(&dsi_ctx, 0x0000, 2160 - 1); in sony_td4353_jdi_on()
56 mipi_dsi_dcs_set_tear_scanline_multi(&dsi_ctx, 0); in sony_td4353_jdi_on()
57 mipi_dsi_dcs_set_tear_on_multi(&dsi_ctx, MIPI_DSI_DCS_TEAR_MODE_VBLANK); in sony_td4353_jdi_on()
58 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_SET_ADDRESS_MODE, 0x00); in sony_td4353_jdi_on()
60 mipi_dsi_dcs_set_pixel_format_multi(&dsi_ctx, 0x77); in sony_td4353_jdi_on()
61 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_SET_PARTIAL_ROWS, in sony_td4353_jdi_on()
64 mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); in sony_td4353_jdi_on()
65 mipi_dsi_msleep(&dsi_ctx, 70); in sony_td4353_jdi_on()
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H A Dpanel-samsung-ltl106hl02.c42 struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; in samsung_ltl106hl02_prepare() local
55 mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); in samsung_ltl106hl02_prepare()
56 mipi_dsi_msleep(&dsi_ctx, 70); in samsung_ltl106hl02_prepare()
58 mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); in samsung_ltl106hl02_prepare()
59 mipi_dsi_msleep(&dsi_ctx, 5); in samsung_ltl106hl02_prepare()
61 return dsi_ctx.accum_err; in samsung_ltl106hl02_prepare()
67 struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; in samsung_ltl106hl02_unprepare() local
69 mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); in samsung_ltl106hl02_unprepare()
70 mipi_dsi_msleep(&dsi_ctx, 50); in samsung_ltl106hl02_unprepare()
71 mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); in samsung_ltl106hl02_unprepare()
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H A Dpanel-visionox-rm69299.c195 struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; in visionox_rm69299_unprepare() local
199 mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); in visionox_rm69299_unprepare()
202 mipi_dsi_msleep(&dsi_ctx, 120); in visionox_rm69299_unprepare()
204 mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); in visionox_rm69299_unprepare()
212 struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; in visionox_rm69299_prepare() local
222 mipi_dsi_dcs_write_buffer_multi(&dsi_ctx, &ctx->desc->init_seq[i * 2], 2); in visionox_rm69299_prepare()
224 mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); in visionox_rm69299_prepare()
227 mipi_dsi_msleep(&dsi_ctx, 120); in visionox_rm69299_prepare()
229 mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); in visionox_rm69299_prepare()
232 mipi_dsi_msleep(&dsi_ctx, 120); in visionox_rm69299_prepare()
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