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Searched refs:dsc_dpcd (Results 1 – 4 of 4) sorted by relevance

/linux/include/drm/display/
H A Ddrm_dp_helper.h210 u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
212 u32 drm_dp_dsc_sink_slice_count_mask(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
214 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
216 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
219 int drm_dp_dsc_sink_max_slice_throughput(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
226 drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) in drm_dp_sink_supports_dsc()
228 return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] & in drm_dp_sink_supports_dsc()
233 drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) in drm_edp_dsc_sink_output_bpp()
235 return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] | in drm_edp_dsc_sink_output_bpp()
236 ((dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] & in drm_edp_dsc_sink_output_bpp()
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_dp.c838 return drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, true); in intel_dp_dsc_min_slice_count()
859 tp_rgb_yuv444 = drm_dp_dsc_sink_max_slice_throughput(connector->dp.dsc_dpcd, in intel_dp_dsc_min_slice_count()
861 tp_yuv422_420 = drm_dp_dsc_sink_max_slice_throughput(connector->dp.dsc_dpcd, in intel_dp_dsc_min_slice_count()
882 max_slice_width = drm_dp_dsc_sink_max_slice_width(connector->dp.dsc_dpcd); in intel_dp_dsc_min_slice_count()
908 drm_dp_dsc_sink_slice_count_mask(connector->dp.dsc_dpcd, is_edp); in intel_dp_dsc_get_slice_config()
1262 if (!drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd)) in intel_dp_has_dsc()
1383 drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4; in intel_dp_mode_valid_format()
1781 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, in align_min_sink_dsc_input_bpp()
1798 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, in align_max_sink_dsc_input_bpp()
1829 static int intel_dp_sink_dsc_version_minor(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) in intel_dp_sink_dsc_version_minor()
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H A Dintel_display_types.h561 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]; member
/linux/drivers/gpu/drm/display/
H A Ddrm_dp_helper.c2688 u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) in drm_dp_dsc_sink_bpp_incr()
2690 u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT]; in drm_dp_dsc_sink_bpp_incr()
2735 u32 drm_dp_dsc_sink_slice_count_mask(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], in drm_dp_dsc_sink_slice_count_mask()
2738 u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT]; in drm_dp_dsc_sink_slice_count_mask()
2743 u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT]; in drm_dp_dsc_sink_slice_count_mask()
2790 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], in drm_dp_dsc_sink_max_slice_count()
2793 return fls(drm_dp_dsc_sink_slice_count_mask(dsc_dpcd, is_edp)); in drm_dp_dsc_sink_max_slice_count()
2812 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) in drm_dp_dsc_sink_line_buf_depth()
2814 u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH - DP_DSC_SUPPORT]; in drm_dp_dsc_sink_line_buf_depth()
2858 int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], in drm_dp_dsc_sink_supported_input_bpcs()
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