| /linux/drivers/gpu/drm/amd/display/dc/dsc/ |
| H A D | rc_calc_dpi.c | 71 static void copy_rc_to_cfg(struct drm_dsc_config *dsc_cfg, const struct rc_params *rc) in copy_rc_to_cfg() argument
75 dsc_cfg->rc_quant_incr_limit0 = rc->rc_quant_incr_limit0; in copy_rc_to_cfg()
76 dsc_cfg->rc_quant_incr_limit1 = rc->rc_quant_incr_limit1; in copy_rc_to_cfg()
77 dsc_cfg->initial_offset = rc->initial_fullness_offset; in copy_rc_to_cfg()
78 dsc_cfg->initial_xmit_delay = rc->initial_xmit_delay; in copy_rc_to_cfg()
79 dsc_cfg->first_line_bpg_offset = rc->first_line_bpg_offset; in copy_rc_to_cfg()
80 dsc_cfg->second_line_bpg_offset = rc->second_line_bpg_offset; in copy_rc_to_cfg()
81 dsc_cfg->flatness_min_qp = rc->flatness_min_qp; in copy_rc_to_cfg()
82 dsc_cfg->flatness_max_qp = rc->flatness_max_qp; in copy_rc_to_cfg()
84 dsc_cfg->rc_range_params[i].range_min_qp = rc->qp_min[i]; in copy_rc_to_cfg()
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| H A D | dc_dsc.c | 102 timing->dsc_cfg.bits_per_pixel, in dc_bandwidth_in_kbps_from_timing()
103 timing->dsc_cfg.num_slices_h, in dc_bandwidth_in_kbps_from_timing()
104 timing->dsc_cfg.is_dp); in dc_bandwidth_in_kbps_from_timing()
195 struct dc_dsc_config *dsc_cfg);
1050 struct dc_dsc_config *dsc_cfg) in setup_dsc_config() argument
1065 memset(dsc_cfg, 0, sizeof(struct dc_dsc_config)); in setup_dsc_config()
1087 dsc_cfg->ycbcr422_simple = false; in setup_dsc_config()
1102 dsc_cfg->ycbcr422_simple = is_dsc_possible; in setup_dsc_config()
1231 dsc_cfg->num_slices_h = num_slices_h; in setup_dsc_config()
1257 dsc_cfg->num_slices_v = pic_height / slice_height; in setup_dsc_config()
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| /linux/drivers/gpu/drm/amd/display/dc/dsc/dcn20/ |
| H A D | dcn20_dsc.c | 167 bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg) in dsc2_validate_stream() argument
172 if (dsc_cfg->pic_width > dsc20->max_image_width) in dsc2_validate_stream()
175 return dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, &dsc_optc_cfg); in dsc2_validate_stream()
190 void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, in dsc2_set_config() argument
197 dsc_config_log(dsc, dsc_cfg); in dsc2_set_config()
198 is_config_ok = dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, dsc_optc_cfg); in dsc2_set_config()
206 bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, u… in dsc2_get_packed_pps() argument
216 dsc_config_log(dsc, dsc_cfg); in dsc2_get_packed_pps()
218 is_config_ok = dsc_prepare_config(dsc_cfg, &dsc_reg_vals, &dsc_optc_cfg); in dsc2_get_packed_pps()
370 bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values *dsc_reg_vals, in dsc_prepare_config() argument
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| /linux/drivers/gpu/drm/amd/display/dc/link/ |
| H A D | link_dpms.c | 694 struct dsc_config dsc_cfg; in link_set_dsc_on_stream() local
699 …dsc_cfg.pic_width = (stream->timing.h_addressable + pipe_ctx->dsc_padding_params.dsc_hactive_paddi… in link_set_dsc_on_stream()
701 …dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v… in link_set_dsc_on_stream()
702 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; in link_set_dsc_on_stream()
703 dsc_cfg.color_depth = stream->timing.display_color_depth; in link_set_dsc_on_stream()
704 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; in link_set_dsc_on_stream()
705 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; in link_set_dsc_on_stream()
706 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); in link_set_dsc_on_stream()
707 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; in link_set_dsc_on_stream()
708 dsc_cfg.dsc_padding = 0; in link_set_dsc_on_stream()
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| /linux/drivers/gpu/drm/amd/display/dc/dsc/dcn401/ |
| H A D | dcn401_dsc.c | 118 bool dsc401_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg) in dsc401_validate_stream() argument
123 if (dsc_cfg->pic_width > dsc401->max_image_width) in dsc401_validate_stream()
126 return dsc_prepare_config(dsc_cfg, &dsc401->reg_vals, &dsc_optc_cfg); in dsc401_validate_stream()
129 void dsc401_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, in dsc401_set_config() argument
136 dsc_config_log(dsc, dsc_cfg); in dsc401_set_config()
137 is_config_ok = dsc_prepare_config(dsc_cfg, &dsc401->reg_vals, dsc_optc_cfg); in dsc401_set_config()
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| H A D | dcn401_dsc.h | 338 bool dsc401_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg…
339 void dsc401_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_stream.c | 121 memset(&stream->timing.dsc_cfg, 0, sizeof(stream->timing.dsc_cfg)); in dc_stream_construct()
122 stream->timing.dsc_cfg.num_slices_h = 0; in dc_stream_construct()
123 stream->timing.dsc_cfg.num_slices_v = 0; in dc_stream_construct()
124 stream->timing.dsc_cfg.bits_per_pixel = 128; in dc_stream_construct()
125 stream->timing.dsc_cfg.block_pred_enable = 1; in dc_stream_construct()
126 stream->timing.dsc_cfg.linebuf_depth = 9; in dc_stream_construct()
127 stream->timing.dsc_cfg.version_minor = 2; in dc_stream_construct()
128 stream->timing.dsc_cfg.ycbcr422_simple = 0; in dc_stream_construct()
932 stream->timing.dsc_cfg.mst_pbn); in dc_stream_log()
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| H A D | dc_hw_sequencer.c | 2286 struct dsc_config *dsc_cfg = params->dsc_set_config_params.dsc_cfg; in hwss_dsc_set_config() local
2290 dsc->funcs->dsc_set_config(dsc, dsc_cfg, dsc_optc_cfg); in hwss_dsc_set_config()
2355 struct dsc_config dsc_cfg; in hwss_dsc_calculate_and_set_config() local
2360 …dsc_cfg.pic_width = (stream->timing.h_addressable + top_pipe->dsc_padding_params.dsc_hactive_paddi… in hwss_dsc_calculate_and_set_config()
2362 …dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v… in hwss_dsc_calculate_and_set_config()
2363 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; in hwss_dsc_calculate_and_set_config()
2364 dsc_cfg.color_depth = stream->timing.display_color_depth; in hwss_dsc_calculate_and_set_config()
2365 dsc_cfg.is_odm = top_pipe->next_odm_pipe ? true : false; in hwss_dsc_calculate_and_set_config()
2366 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; in hwss_dsc_calculate_and_set_config()
2367 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; in hwss_dsc_calculate_and_set_config()
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| /linux/drivers/gpu/drm/panel/ |
| H A D | panel-himax-hx83121a.c | 47 const struct drm_dsc_config *dsc_cfg; member
617 ctx->dsc = *desc->dsc_cfg; in himax_probe()
692 .dsc_cfg = &ppc357db1_4_dsc_cfg,
711 .dsc_cfg = &ppc357db1_4_dsc_cfg,
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| /linux/include/drm/display/ |
| H A D | drm_dsc_helper.h | 25 const struct drm_dsc_config *dsc_cfg);
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| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_mst_types.c | 924 memset(¶ms[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg)); in set_dsc_configs_from_fairness_vars()
932 ¶ms[i].timing->dsc_cfg)) { in set_dsc_configs_from_fairness_vars()
936 params[i].timing->dsc_cfg.bits_per_pixel = params[i].bpp_overwrite; in set_dsc_configs_from_fairness_vars()
938 params[i].timing->dsc_cfg.bits_per_pixel = vars[i + k].bpp_x16; in set_dsc_configs_from_fairness_vars()
941 params[i].timing->dsc_cfg.num_slices_h = params[i].num_slices_h; in set_dsc_configs_from_fairness_vars()
944 params[i].timing->dsc_cfg.num_slices_v = params[i].num_slices_v; in set_dsc_configs_from_fairness_vars()
948 params[i].timing->dsc_cfg.mst_pbn = vars[i + k].pbn; in set_dsc_configs_from_fairness_vars()
961 params[i].timing->dsc_cfg.bits_per_pixel, in set_dsc_configs_from_fairness_vars()
1954 &stream->timing.dsc_cfg)) { in dm_dp_mst_is_port_support_mode()
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| H A D | amdgpu_dm.c | 7193 struct dc_dsc_config dsc_cfg = {0}; in apply_dsc_policy_for_edp() local
7225 &dsc_cfg)) { in apply_dsc_policy_for_edp()
7226 stream->timing.dsc_cfg = dsc_cfg; in apply_dsc_policy_for_edp()
7228 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16; in apply_dsc_policy_for_edp()
7240 &dsc_cfg)) { in apply_dsc_policy_for_edp()
7241 stream->timing.dsc_cfg = dsc_cfg; in apply_dsc_policy_for_edp()
7283 &stream->timing.dsc_cfg)) { in apply_dsc_policy_for_stream()
7303 &stream->timing.dsc_cfg)) { in apply_dsc_policy_for_stream()
7316 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h; in apply_dsc_policy_for_stream()
7319 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v; in apply_dsc_policy_for_stream()
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc_dsc.h | 88 struct dc_dsc_config *dsc_cfg);
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| H A D | dcn20_resource.c | 1689 struct dsc_config dsc_cfg; in dcn20_validate_dsc() local
1700 …dsc_cfg.pic_width = (stream->timing.h_addressable + pipe_ctx->dsc_padding_params.dsc_hactive_paddi… in dcn20_validate_dsc()
1702 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top in dcn20_validate_dsc()
1704 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; in dcn20_validate_dsc()
1705 dsc_cfg.color_depth = stream->timing.display_color_depth; in dcn20_validate_dsc()
1706 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; in dcn20_validate_dsc()
1707 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; in dcn20_validate_dsc()
1708 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; in dcn20_validate_dsc()
1709 dsc_cfg.dsc_padding = 0; in dcn20_validate_dsc()
1711 if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg)) in dcn20_validate_dsc()
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| /linux/drivers/gpu/drm/amd/display/modules/power/ |
| H A D | power_helpers.c | 971 !stream->timing.dsc_cfg.num_slices_v) in psr_su_set_dsc_slice_height()
977 if (stream->timing.dsc_cfg.num_slices_v == 0) in psr_su_set_dsc_slice_height()
980 slice_height = pic_height / stream->timing.dsc_cfg.num_slices_v; in psr_su_set_dsc_slice_height()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/ |
| H A D | dml21_translation_helper.c | 155 timing->dsc.overrides.num_slices = stream->timing.dsc_cfg.num_slices_h; in populate_dml21_timing_config_from_stream_state()
156 timing->dsc.dsc_compressed_bpp_x16 = stream->timing.dsc_cfg.bits_per_pixel; in populate_dml21_timing_config_from_stream_state()
226 if (stream->timing.flags.DSC && !stream->timing.dsc_cfg.ycbcr422_simple) in populate_dml21_output_config_from_stream_state()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | dml2_translation_helper.c | 794 out->DSCSlices[location] = in->timing.dsc_cfg.num_slices_h; in populate_dml_output_cfg_from_stream_state()
856 if (in->timing.flags.DSC && !in->timing.dsc_cfg.ycbcr422_simple) in populate_dml_output_cfg_from_stream_state()
869 out->OutputBpp[location] = in->timing.dsc_cfg.bits_per_pixel / 16.0; in populate_dml_output_cfg_from_stream_state()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.c | 1374 pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h; in dcn20_populate_dml_pipes_from_context()
1515 !res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.ycbcr422_simple) in dcn20_populate_dml_pipes_from_context()
1527 …pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.… in dcn20_populate_dml_pipes_from_context()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/ |
| H A D | dce110_hwseq.c | 1392 bpp = crtc_timing->dsc_cfg.bits_per_pixel; in populate_audio_dp_link_info()
1490 stream->timing.dsc_cfg.bits_per_pixel; in build_audio_output()
1493 stream->timing.dsc_cfg.num_slices_h; in build_audio_output()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 1563 int num_slices_h = stream->timing.dsc_cfg.num_slices_h / opp_cnt; in dcn401_add_dsc_sequence_for_odm_change()
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