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Searched refs:dsc_cfg (Results 1 – 24 of 24) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dsc/
H A Drc_calc_dpi.c71 static void copy_rc_to_cfg(struct drm_dsc_config *dsc_cfg, const struct rc_params *rc) in copy_rc_to_cfg() argument
75 dsc_cfg->rc_quant_incr_limit0 = rc->rc_quant_incr_limit0; in copy_rc_to_cfg()
76 dsc_cfg->rc_quant_incr_limit1 = rc->rc_quant_incr_limit1; in copy_rc_to_cfg()
77 dsc_cfg->initial_offset = rc->initial_fullness_offset; in copy_rc_to_cfg()
78 dsc_cfg->initial_xmit_delay = rc->initial_xmit_delay; in copy_rc_to_cfg()
79 dsc_cfg->first_line_bpg_offset = rc->first_line_bpg_offset; in copy_rc_to_cfg()
80 dsc_cfg->second_line_bpg_offset = rc->second_line_bpg_offset; in copy_rc_to_cfg()
81 dsc_cfg->flatness_min_qp = rc->flatness_min_qp; in copy_rc_to_cfg()
82 dsc_cfg->flatness_max_qp = rc->flatness_max_qp; in copy_rc_to_cfg()
84 dsc_cfg->rc_range_params[i].range_min_qp = rc->qp_min[i]; in copy_rc_to_cfg()
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H A Ddsc.h102 …ol (*dsc_validate_stream)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);
103 void (*dsc_set_config)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
105 bool (*dsc_get_packed_pps)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn20/
H A Ddcn20_dsc.c166 bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg) in dsc2_validate_stream() argument
171 if (dsc_cfg->pic_width > dsc20->max_image_width) in dsc2_validate_stream()
174 return dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, &dsc_optc_cfg); in dsc2_validate_stream()
189 void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, in dsc2_set_config() argument
196 dsc_config_log(dsc, dsc_cfg); in dsc2_set_config()
197 is_config_ok = dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, dsc_optc_cfg); in dsc2_set_config()
205 bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, u… in dsc2_get_packed_pps() argument
215 dsc_config_log(dsc, dsc_cfg); in dsc2_get_packed_pps()
217 is_config_ok = dsc_prepare_config(dsc_cfg, &dsc_reg_vals, &dsc_optc_cfg); in dsc2_get_packed_pps()
369 bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values *dsc_reg_vals, in dsc_prepare_config() argument
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H A Ddcn20_dsc.h575 bool dsc_prepare_config(const struct dsc_config *dsc_cfg,
599 const struct dsc_config *dsc_cfg,
603 bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);
604 void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
/linux/drivers/gpu/drm/display/
H A Ddrm_dsc_helper.c99 const struct drm_dsc_config *dsc_cfg) in drm_dsc_pps_payload_pack() argument
111 dsc_cfg->dsc_version_minor | in drm_dsc_pps_payload_pack()
112 dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT; in drm_dsc_pps_payload_pack()
118 dsc_cfg->line_buf_depth | in drm_dsc_pps_payload_pack()
119 dsc_cfg->bits_per_component << DSC_PPS_BPC_SHIFT; in drm_dsc_pps_payload_pack()
123 ((dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >> in drm_dsc_pps_payload_pack()
125 dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT | in drm_dsc_pps_payload_pack()
126 dsc_cfg->simple_422 << DSC_PPS_SIMPLE422_SHIFT | in drm_dsc_pps_payload_pack()
127 dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT | in drm_dsc_pps_payload_pack()
128 dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT; in drm_dsc_pps_payload_pack()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn314/
H A Ddcn314_hwseq.c84 struct dsc_config dsc_cfg; in update_dsc_on_stream() local
89 …dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.… in update_dsc_on_stream()
90 …dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v… in update_dsc_on_stream()
91 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; in update_dsc_on_stream()
92 dsc_cfg.color_depth = stream->timing.display_color_depth; in update_dsc_on_stream()
93 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; in update_dsc_on_stream()
94 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; in update_dsc_on_stream()
95 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); in update_dsc_on_stream()
96 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; in update_dsc_on_stream()
98 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); in update_dsc_on_stream()
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/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn401/
H A Ddcn401_dsc.c20 …ol dsc401_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);
21 …tic void dsc401_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
137 …ool dsc401_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg) in dsc401_validate_stream() argument
142 if (dsc_cfg->pic_width > dsc401->max_image_width) in dsc401_validate_stream()
145 return dsc_prepare_config(dsc_cfg, &dsc401->reg_vals, &dsc_optc_cfg); in dsc401_validate_stream()
148 …tic void dsc401_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, in dsc401_set_config() argument
155 dsc_config_log(dsc, dsc_cfg); in dsc401_set_config()
156 is_config_ok = dsc_prepare_config(dsc_cfg, &dsc401->reg_vals, dsc_optc_cfg); in dsc401_set_config()
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_stream.c112 memset(&stream->timing.dsc_cfg, 0, sizeof(stream->timing.dsc_cfg)); in dc_stream_construct()
113 stream->timing.dsc_cfg.num_slices_h = 0; in dc_stream_construct()
114 stream->timing.dsc_cfg.num_slices_v = 0; in dc_stream_construct()
115 stream->timing.dsc_cfg.bits_per_pixel = 128; in dc_stream_construct()
116 stream->timing.dsc_cfg.block_pred_enable = 1; in dc_stream_construct()
117 stream->timing.dsc_cfg.linebuf_depth = 9; in dc_stream_construct()
118 stream->timing.dsc_cfg.version_minor = 2; in dc_stream_construct()
119 stream->timing.dsc_cfg.ycbcr422_simple = 0; in dc_stream_construct()
828 stream->timing.dsc_cfg.mst_pbn); in dc_stream_log()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
H A Ddcn35_hwseq.c335 struct dsc_config dsc_cfg; in update_dsc_on_stream() local
353 …dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.… in update_dsc_on_stream()
354 …dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v… in update_dsc_on_stream()
355 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; in update_dsc_on_stream()
356 dsc_cfg.color_depth = stream->timing.display_color_depth; in update_dsc_on_stream()
357 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; in update_dsc_on_stream()
358 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; in update_dsc_on_stream()
359 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); in update_dsc_on_stream()
360 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; in update_dsc_on_stream()
362 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); in update_dsc_on_stream()
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/linux/include/drm/display/
H A Ddrm_dsc_helper.h25 const struct drm_dsc_config *dsc_cfg);
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_mst_types.c850 memset(&params[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg)); in set_dsc_configs_from_fairness_vars()
858 &params[i].timing->dsc_cfg)) { in set_dsc_configs_from_fairness_vars()
862 params[i].timing->dsc_cfg.bits_per_pixel = params[i].bpp_overwrite; in set_dsc_configs_from_fairness_vars()
864 params[i].timing->dsc_cfg.bits_per_pixel = vars[i + k].bpp_x16; in set_dsc_configs_from_fairness_vars()
867 params[i].timing->dsc_cfg.num_slices_h = params[i].num_slices_h; in set_dsc_configs_from_fairness_vars()
870 params[i].timing->dsc_cfg.num_slices_v = params[i].num_slices_v; in set_dsc_configs_from_fairness_vars()
874 params[i].timing->dsc_cfg.mst_pbn = vars[i + k].pbn; in set_dsc_configs_from_fairness_vars()
887 params[i].timing->dsc_cfg.bits_per_pixel, in set_dsc_configs_from_fairness_vars()
1855 &stream->timing.dsc_cfg)) { in dm_dp_mst_is_port_support_mode()
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_dsc.h87 struct dc_dsc_config *dsc_cfg);
H A Ddc_hw_types.h977 struct dc_dsc_config dsc_cfg; member
/linux/drivers/gpu/drm/amd/display/dc/link/
H A Dlink_validation.c128 if (timing->flags.DSC && !timing->dsc_cfg.is_frl) in dp_active_dongle_validate_timing()
/linux/drivers/gpu/drm/amd/display/modules/power/
H A Dpower_helpers.c955 !stream->timing.dsc_cfg.num_slices_v) in psr_su_set_dsc_slice_height()
961 if (stream->timing.dsc_cfg.num_slices_v == 0) in psr_su_set_dsc_slice_height()
964 slice_height = pic_height / stream->timing.dsc_cfg.num_slices_v; in psr_su_set_dsc_slice_height()
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn32/
H A Ddcn32_dio_stream_encoder.c240 && !timing->dsc_cfg.ycbcr422_simple); in is_two_pixels_per_containter()
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn35/
H A Ddcn35_dio_stream_encoder.c272 && !timing->dsc_cfg.ycbcr422_simple); in is_two_pixels_per_containter()
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn314/
H A Ddcn314_dio_stream_encoder.c282 && !timing->dsc_cfg.ycbcr422_simple); in is_two_pixels_per_containter()
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn20/
H A Ddcn20_stream_encoder.c464 && !timing->dsc_cfg.ycbcr422_simple); in is_two_pixels_per_containter()
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn31/
H A Ddcn31_dccg.c566 && !params->timing->dsc_cfg.ycbcr422_simple)) { in dccg31_set_dtbclk_dto()
/linux/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddml2_translation_helper.c743 out->DSCSlices[location] = in->timing.dsc_cfg.num_slices_h; in populate_dml_output_cfg_from_stream_state()
805 if (in->timing.flags.DSC && !in->timing.dsc_cfg.ycbcr422_simple) in populate_dml_output_cfg_from_stream_state()
818 out->OutputBpp[location] = in->timing.dsc_cfg.bits_per_pixel / 16.0; in populate_dml_output_cfg_from_stream_state()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c1374 pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h; in dcn20_populate_dml_pipes_from_context()
1515 !res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.ycbcr422_simple) in dcn20_populate_dml_pipes_from_context()
1527 …pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.… in dcn20_populate_dml_pipes_from_context()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/
H A Ddce110_hwseq.c1326 bpp = crtc_timing->dsc_cfg.bits_per_pixel; in populate_audio_dp_link_info()
1424 stream->timing.dsc_cfg.bits_per_pixel; in build_audio_output()
1427 stream->timing.dsc_cfg.num_slices_h; in build_audio_output()
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn10/
H A Ddcn10_optc.c1565 && !timing->dsc_cfg.ycbcr422_simple); in optc1_is_two_pixels_per_container()