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Searched refs:dsc (Results 1 – 25 of 35) sorted by relevance

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/linux/drivers/gpu/drm/panel/
H A Dpanel-visionox-rm692e5.c27 struct drm_dsc_config dsc; member
209 drm_dsc_pps_payload_pack(&pps, &ctx->dsc); in visionox_rm692e5_prepare()
396 dsi->dsc = &ctx->dsc; in visionox_rm692e5_probe()
397 ctx->dsc.dsc_version_major = 1; in visionox_rm692e5_probe()
398 ctx->dsc.dsc_version_minor = 1; in visionox_rm692e5_probe()
399 ctx->dsc.slice_height = 20; in visionox_rm692e5_probe()
400 ctx->dsc.slice_width = 540; in visionox_rm692e5_probe()
401 ctx->dsc.slice_count = 1080 / ctx->dsc.slice_width; in visionox_rm692e5_probe()
402 ctx->dsc.bits_per_component = 10; in visionox_rm692e5_probe()
403 ctx->dsc.bits_per_pixel = 8 << 4; in visionox_rm692e5_probe()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn401/
H A Ddcn401_dsc.h13 #define TO_DCN401_DSC(dsc)\ argument
14 container_of(dsc, struct dcn401_dsc, base)
328 void dsc401_construct(struct dcn401_dsc *dsc,
337 void dsc401_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);
338 bool dsc401_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg…
339 void dsc401_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
341 void dsc401_enable(struct display_stream_compressor *dsc, int opp_pipe);
342 void dsc401_disable(struct display_stream_compressor *dsc);
343 void dsc401_disconnect(struct display_stream_compressor *dsc);
344 void dsc401_wait_disconnect_pending_clear(struct display_stream_compressor *dsc);
/linux/drivers/gpu/drm/tests/
H A Ddrm_dp_mst_helper_test.c18 const bool dsc; member
26 .dsc = false,
32 .dsc = false,
38 .dsc = false,
44 .dsc = true,
50 .dsc = true,
65 sprintf(desc, "Clock %d BPP %d DSC %s", t->clock, t->bpp, t->dsc ? "enabled" : "disabled"); in dp_mst_calc_pbn_mode_desc()
/linux/drivers/net/ethernet/broadcom/
H A Dsb1250-mac.c773 struct sbdmadscr *dsc; in sbdma_add_rcvbuffer() local
780 dsc = d->sbdma_addptr; in sbdma_add_rcvbuffer()
837 dsc->dscr_a = virt_to_phys(sb_new->data) | in sbdma_add_rcvbuffer()
840 dsc->dscr_a = virt_to_phys(sb_new->data) | in sbdma_add_rcvbuffer()
846 dsc->dscr_b = 0; in sbdma_add_rcvbuffer()
852 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb_new; in sbdma_add_rcvbuffer()
887 struct sbdmadscr *dsc; in sbdma_add_txbuffer() local
895 dsc = d->sbdma_addptr; in sbdma_add_txbuffer()
926 dsc->dscr_a = phys | in sbdma_add_txbuffer()
935 dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) | in sbdma_add_txbuffer()
[all …]
/linux/include/drm/display/
H A Ddrm_dsc_helper.h30 u8 drm_dsc_initial_scale_value(const struct drm_dsc_config *dsc);
31 u32 drm_dsc_flatness_det_thresh(const struct drm_dsc_config *dsc);
/linux/drivers/gpu/drm/i915/display/
H A Dintel_dp_mst.c145 bool dsc) in intel_dp_mst_max_dpt_bpp() argument
151 if (!intel_dp_is_uhbr(crtc_state) || DISPLAY_VER(display) >= 20 || !dsc) in intel_dp_mst_max_dpt_bpp()
252 int min_bpp_x16, int max_bpp_x16, int bpp_step_x16, bool dsc) in intel_dp_mtp_tu_compute_config() argument
267 drm_WARN_ON(display->drm, !dsc && (fxp_q4_to_frac(min_bpp_x16) || in intel_dp_mtp_tu_compute_config()
293 crtc_state->fec_enable = intel_dp_needs_8b10b_fec(crtc_state, dsc); in intel_dp_mtp_tu_compute_config()
301 if (crtc_state->fec_enable && dsc && in intel_dp_mtp_tu_compute_config()
305 max_dpt_bpp_x16 = fxp_q4_from_int(intel_dp_mst_max_dpt_bpp(crtc_state, dsc)); in intel_dp_mtp_tu_compute_config()
315 if (dsc) { in intel_dp_mtp_tu_compute_config()
332 if (dsc && !intel_dp_dsc_valid_compressed_bpp(intel_dp, bpp_x16)) { in intel_dp_mtp_tu_compute_config()
338 link_bpp_x16 = dsc ? bpp_x16 : in intel_dp_mtp_tu_compute_config()
[all …]
/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_dsc.h37 struct drm_dsc_config *dsc,
47 struct drm_dsc_config *dsc);
H A Ddpu_rm.c169 const struct dpu_dsc_cfg *dsc = &cat->dsc[i]; in dpu_rm_init() local
172 hw = dpu_hw_dsc_init_1_2(dev, dsc, mmio); in dpu_rm_init()
174 hw = dpu_hw_dsc_init(dev, dsc, mmio, cat->mdss_ver); in dpu_rm_init()
181 rm->dsc_blks[dsc->id - DSC_0] = &hw->base; in dpu_rm_init()
H A Ddpu_hw_ctl.h59 unsigned int dsc; member
/linux/drivers/net/ethernet/mellanox/mlx5/core/en_accel/
H A Dktls_stats.c50 #define MLX5E_READ_CTR_ATOMIC64(ptr, dsc, i) \ argument
51 atomic64_read((atomic64_t *)((char *)(ptr) + (dsc)[i].offset))
H A Dipsec_stats.c61 #define MLX5E_READ_CTR_ATOMIC64(ptr, dsc, i) \ argument
62 atomic64_read((atomic64_t *)((char *)(ptr) + (dsc)[i].offset))
/linux/arch/mips/mm/
H A Dcerr-sb1.c466 struct dc_state *dsc = dc_states; in dc_state_str() local
467 while (dsc->val != 0xff) { in dc_state_str()
468 if (dsc->val == state) in dc_state_str()
470 dsc++; in dc_state_str()
472 return dsc->name; in dc_state_str()
/linux/sound/pci/ctxfi/
H A Dctdaio.c446 struct daio_desc dsc = {0}; in dao_rsc_reinit() local
448 dsc.type = dao->daio.type; in dao_rsc_reinit()
449 dsc.msr = desc->msr; in dao_rsc_reinit()
450 dsc.passthru = desc->passthru; in dao_rsc_reinit()
451 dsc.output = dao->daio.output; in dao_rsc_reinit()
453 return dao_rsc_init(dao, &dsc, mgr); in dao_rsc_reinit()
/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn35/
H A Ddcn35_dsc.h50 void dsc35_construct(struct dcn20_dsc *dsc,
/linux/tools/perf/util/
H A Ddlfilter.c593 const char *dsc; in get_filter_desc() local
596 dsc = desc_fn(&long_dsc); in get_filter_desc()
597 if (dsc) in get_filter_desc()
598 *desc = strdup(dsc); in get_filter_desc()
/linux/drivers/usb/atm/
H A Dueagle-atm.c1946 struct cmv_dsc_e1 *dsc = &sc->cmv_dsc.e1; in uea_dispatch_cmv_e1() local
1958 if (cmv->bFunction != dsc->function) { in uea_dispatch_cmv_e1()
1961 cmv->wIndex = cpu_to_le16(dsc->idx); in uea_dispatch_cmv_e1()
1962 put_unaligned_le32(dsc->address, in uea_dispatch_cmv_e1()
1964 cmv->wOffsetAddress = cpu_to_le16(dsc->offset); in uea_dispatch_cmv_e1()
1976 if (le16_to_cpu(cmv->wIndex) != dsc->idx || in uea_dispatch_cmv_e1()
1977 get_unaligned_le32(&cmv->dwSymbolicAddress) != dsc->address || in uea_dispatch_cmv_e1()
1978 le16_to_cpu(cmv->wOffsetAddress) != dsc->offset) in uea_dispatch_cmv_e1()
2003 struct cmv_dsc_e4 *dsc = &sc->cmv_dsc.e4; in uea_dispatch_cmv_e4() local
2011 if (be16_to_cpu(cmv->wFunction) != dsc->function) in uea_dispatch_cmv_e4()
[all …]
/linux/drivers/media/platform/samsung/s5p-mfc/
H A Ds5p_mfc_opr_v5.c40 ctx->dsc.size = buf_size->dsc; in s5p_mfc_alloc_dec_temp_buffers_v5()
41 ret = s5p_mfc_alloc_priv_buf(dev, BANK_L_CTX, &ctx->dsc); in s5p_mfc_alloc_dec_temp_buffers_v5()
47 BUG_ON(ctx->dsc.dma & ((1 << MFC_BANK1_ALIGN_ORDER) - 1)); in s5p_mfc_alloc_dec_temp_buffers_v5()
48 memset(ctx->dsc.virt, 0, ctx->dsc.size); in s5p_mfc_alloc_dec_temp_buffers_v5()
57 s5p_mfc_release_priv_buf(ctx->dev, &ctx->dsc); in s5p_mfc_release_dec_desc_buffer_v5()
350 mfc_write(dev, OFFSETA(ctx->dsc.dma), S5P_FIMV_SI_CH0_DESC_ADR); in s5p_mfc_set_dec_desc_buffer()
351 mfc_write(dev, buf_size->dsc, S5P_FIMV_SI_CH0_DESC_SIZE); in s5p_mfc_set_dec_desc_buffer()
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/
H A Ddml2_core_utils.c341 …if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.ena… in dml2_core_utils_get_stream_output_bpp()
357 …>stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_… in dml2_core_utils_get_stream_output_bpp()
358 …>stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.dsc_compressed_bpp_… in dml2_core_utils_get_stream_output_bpp()
364 …display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable); in dml2_core_utils_get_stream_output_bpp()
/linux/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5_cfg.h109 struct mdp5_sub_block dsc; member
/linux/drivers/gpu/drm/amd/display/dc/
H A DMakefile25 DC_LIBS = basics bios dml clk_mgr dce gpio hwss irq link dsc resource optc dpp hubbub dccg hubp dio…
/linux/arch/alpha/include/asm/
H A Dcore_tsunami.h68 tsunami_64 dsc; member
H A Dcore_titan.h75 titan_64 dsc; member
/linux/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_9_1_sar2130p.h395 .dsc = sar2130p_dsc,
H A Ddpu_9_0_sm8550.h395 .dsc = sm8550_dsc,
/linux/arch/mips/include/asm/octeon/
H A Dcvmx-pciercx-defs.h361 __BITFIELD_FIELD(uint32_t dsc:1,

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