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Searched refs:dsc (Results 1 – 25 of 52) sorted by relevance

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/linux/drivers/gpu/drm/panel/
H A Dpanel-lg-sw43408.c33 struct drm_dsc_config dsc; member
106 drm_dsc_pps_payload_pack(&pps, sw43408->link->dsc); in sw43408_program()
276 ctx->dsc.dsc_version_major = 0x1; in sw43408_probe()
277 ctx->dsc.dsc_version_minor = 0x1; in sw43408_probe()
280 ctx->dsc.slice_height = 16; in sw43408_probe()
281 ctx->dsc.slice_width = 540; in sw43408_probe()
282 ctx->dsc.slice_count = 2; in sw43408_probe()
283 ctx->dsc.bits_per_component = 8; in sw43408_probe()
284 ctx->dsc.bits_per_pixel = 8 << 4; in sw43408_probe()
285 ctx->dsc.block_pred_enable = true; in sw43408_probe()
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H A Dpanel-novatek-nt37801.c23 struct drm_dsc_config dsc; member
146 drm_dsc_pps_payload_pack(&pps, &ctx->dsc); in novatek_nt37801_prepare()
291 dsi->dsc = &ctx->dsc; in novatek_nt37801_probe()
292 ctx->dsc.dsc_version_major = 1; in novatek_nt37801_probe()
293 ctx->dsc.dsc_version_minor = 1; in novatek_nt37801_probe()
294 ctx->dsc.slice_height = 40; in novatek_nt37801_probe()
295 ctx->dsc.slice_width = 720; in novatek_nt37801_probe()
296 ctx->dsc.slice_count = 1440 / ctx->dsc.slice_width; in novatek_nt37801_probe()
297 ctx->dsc.bits_per_component = 8; in novatek_nt37801_probe()
298 ctx->dsc.bits_per_pixel = 8 << 4; /* 4 fractional bits */ in novatek_nt37801_probe()
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/linux/drivers/gpu/drm/amd/display/dc/dsc/
H A DMakefile11 AMD_DISPLAY_FILES += $(addprefix $(AMDDALPATH)/dc/dsc/dcn20/,$(DSC_DCN20))
22 AMD_DISPLAY_FILES += $(addprefix $(AMDDALPATH)/dc/dsc/dcn35/,$(DSC_DCN35))
30 AMD_DISPLAY_FILES += $(addprefix $(AMDDALPATH)/dc/dsc/dcn401/,$(DSC_DCN401))
36 AMD_DAL_DSC = $(addprefix $(AMDDALPATH)/dc/dsc/,$(DSC))
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_dsc.h71 const struct display_stream_compressor *dsc,
81 const struct display_stream_compressor *dsc,
97 void dc_dsc_dump_decoder_caps(const struct display_stream_compressor *dsc,
99 void dc_dsc_dump_encoder_caps(const struct display_stream_compressor *dsc,
/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn401/
H A Ddcn401_dsc.h13 #define TO_DCN401_DSC(dsc)\ argument
14 container_of(dsc, struct dcn401_dsc, base)
328 void dsc401_construct(struct dcn401_dsc *dsc,
337 void dsc401_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);
338 bool dsc401_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg…
339 void dsc401_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
341 void dsc401_enable(struct display_stream_compressor *dsc, int opp_pipe);
342 void dsc401_disable(struct display_stream_compressor *dsc);
343 void dsc401_disconnect(struct display_stream_compressor *dsc);
344 void dsc401_wait_disconnect_pending_clear(struct display_stream_compressor *dsc);
/linux/drivers/gpu/drm/tests/
H A Ddrm_dp_mst_helper_test.c18 const bool dsc; member
26 .dsc = false,
32 .dsc = false,
38 .dsc = false,
44 .dsc = true,
50 .dsc = true,
65 sprintf(desc, "Clock %d BPP %d DSC %s", t->clock, t->bpp, t->dsc ? "enabled" : "disabled"); in dp_mst_calc_pbn_mode_desc()
/linux/drivers/gpu/drm/amd/display/dc/link/
H A Dlink_dpms.c750 static void dsc_optc_config_log(struct display_stream_compressor *dsc, in dsc_optc_config_log() argument
757 DC_LOGGER_INIT(dsc->ctx->logger); in dsc_optc_config_log()
807 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in link_set_dsc_on_stream() local
824 DC_LOGGER_INIT(dsc->ctx->logger); in link_set_dsc_on_stream()
847 dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h); in link_set_dsc_on_stream()
848 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); in link_set_dsc_on_stream()
849 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); in link_set_dsc_on_stream()
851 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; in link_set_dsc_on_stream()
866 dsc_optc_config_log(dsc, &dsc_optc_cfg); in link_set_dsc_on_stream()
878 dsc_optc_config_log(dsc, &dsc_optc_cfg); in link_set_dsc_on_stream()
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/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_hw_sequencer.c2260 struct display_stream_compressor *dsc = params->dsc_set_config_params.dsc; in hwss_dsc_set_config() local
2264 if (dsc && dsc->funcs->dsc_set_config) in hwss_dsc_set_config()
2265 dsc->funcs->dsc_set_config(dsc, dsc_cfg, dsc_optc_cfg); in hwss_dsc_set_config()
2270 struct display_stream_compressor *dsc = params->dsc_enable_params.dsc; in hwss_dsc_enable() local
2273 if (dsc && dsc->funcs->dsc_enable) in hwss_dsc_enable()
2274 dsc->funcs->dsc_enable(dsc, opp_inst); in hwss_dsc_enable()
2301 struct display_stream_compressor *dsc = params->dsc_disconnect_params.dsc; in hwss_dsc_disconnect() local
2303 if (dsc && dsc->funcs->dsc_disconnect) in hwss_dsc_disconnect()
2304 dsc->funcs->dsc_disconnect(dsc); in hwss_dsc_disconnect()
2309 struct display_stream_compressor *dsc = params->dsc_read_state_params.dsc; in hwss_dsc_read_state() local
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/linux/include/drm/display/
H A Ddrm_dsc_helper.h30 u8 drm_dsc_initial_scale_value(const struct drm_dsc_config *dsc);
31 u32 drm_dsc_flatness_det_thresh(const struct drm_dsc_config *dsc);
/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_dsc.h37 struct drm_dsc_config *dsc,
47 struct drm_dsc_config *dsc);
H A Ddpu_encoder.c217 struct drm_dsc_config *dsc; member
303 return dpu_enc->dsc ? true : false; in dpu_encoder_is_dsc_enabled()
668 struct drm_dsc_config *dsc; in dpu_encoder_update_topology() local
676 dsc = dpu_encoder_get_dsc_config(drm_enc); in dpu_encoder_update_topology()
679 if (dsc) { in dpu_encoder_update_topology()
1345 dpu_enc->dsc = dpu_encoder_get_dsc_config(drm_enc); in dpu_encoder_virt_atomic_enable()
1967 dpu_encoder_dsc_initial_line_calc(struct drm_dsc_config *dsc, in dpu_encoder_dsc_initial_line_calc() argument
1972 soft_slice_per_enc = enc_ip_width / dsc->slice_width; in dpu_encoder_dsc_initial_line_calc()
1984 ssm_delay = ((dsc->bits_per_component < 10) ? 84 : 92); in dpu_encoder_dsc_initial_line_calc()
1985 total_pixels = ssm_delay * 3 + dsc->initial_xmit_delay + 47; in dpu_encoder_dsc_initial_line_calc()
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H A Ddpu_rm.c169 const struct dpu_dsc_cfg *dsc = &cat->dsc[i]; in dpu_rm_init() local
172 hw = dpu_hw_dsc_init_1_2(dev, dsc, mmio); in dpu_rm_init()
174 hw = dpu_hw_dsc_init(dev, dsc, mmio, cat->mdss_ver); in dpu_rm_init()
181 rm->dsc_blks[dsc->id - DSC_0] = &hw->base; in dpu_rm_init()
H A Ddpu_encoder_phys_vid.c130 struct drm_dsc_config *dsc = in drm_mode_to_intf_timing_params() local
136 timing->width = timing->width * drm_dsc_get_bpp_int(dsc) / in drm_mode_to_intf_timing_params()
137 (dsc->bits_per_component * 3); in drm_mode_to_intf_timing_params()
310 intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc); in dpu_encoder_phys_vid_setup_timing_engine()
H A Ddpu_kms.c1042 base = dpu_kms->mmio + cat->dsc[i].base; in dpu_kms_mdp_snapshot()
1043 msm_disp_snapshot_add_block(disp_state, cat->dsc[i].len, base, in dpu_kms_mdp_snapshot()
1044 "%s", cat->dsc[i].name); in dpu_kms_mdp_snapshot()
1047 struct dpu_dsc_blk enc = cat->dsc[i].sblk->enc; in dpu_kms_mdp_snapshot()
1048 struct dpu_dsc_blk ctl = cat->dsc[i].sblk->ctl; in dpu_kms_mdp_snapshot()
1051 cat->dsc[i].name, enc.name); in dpu_kms_mdp_snapshot()
1053 cat->dsc[i].name, ctl.name); in dpu_kms_mdp_snapshot()
/linux/drivers/net/ethernet/mellanox/mlx5/core/en_accel/
H A Dktls_stats.c50 #define MLX5E_READ_CTR_ATOMIC64(ptr, dsc, i) \ argument
51 atomic64_read((atomic64_t *)((char *)(ptr) + (dsc)[i].offset))
H A Dipsec_stats.c61 #define MLX5E_READ_CTR_ATOMIC64(ptr, dsc, i) \ argument
62 atomic64_read((atomic64_t *)((char *)(ptr) + (dsc)[i].offset))
/linux/arch/mips/mm/
H A Dcerr-sb1.c466 struct dc_state *dsc = dc_states; in dc_state_str() local
467 while (dsc->val != 0xff) { in dc_state_str()
468 if (dsc->val == state) in dc_state_str()
470 dsc++; in dc_state_str()
472 return dsc->name; in dc_state_str()
/linux/drivers/scsi/qla2xxx/
H A Dqla_mid.c1136 int qla_get_buf(struct scsi_qla_host *vha, struct qla_qpair *qp, struct qla_buf_dsc *dsc) in qla_get_buf() argument
1143 dsc->tag = TAG_FREED; in qla_get_buf()
1170 dsc->buf = qp->buf_pool.buf_array[tag] = buf; in qla_get_buf()
1171 dsc->buf_dma = qp->buf_pool.dma_array[tag] = buf_dma; in qla_get_buf()
1174 dsc->buf = qp->buf_pool.buf_array[tag]; in qla_get_buf()
1175 dsc->buf_dma = qp->buf_pool.dma_array[tag]; in qla_get_buf()
1176 memset(dsc->buf, 0, FCP_CMND_DMA_POOL_SIZE); in qla_get_buf()
1183 dsc->tag = tag; in qla_get_buf()
1242 void qla_put_buf(struct qla_qpair *qp, struct qla_buf_dsc *dsc) in qla_put_buf() argument
1244 if (dsc->tag == TAG_FREED) in qla_put_buf()
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/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn35/
H A Ddcn35_dsc.h50 void dsc35_construct(struct dcn20_dsc *dsc,
/linux/tools/perf/util/
H A Ddlfilter.c594 const char *dsc; in get_filter_desc() local
597 dsc = desc_fn(&long_dsc); in get_filter_desc()
598 if (dsc) in get_filter_desc()
599 *desc = strdup(dsc); in get_filter_desc()
/linux/drivers/gpu/drm/i915/display/
H A Dintel_display.c483 new_crtc_state->dsc.compression_enable) { in intel_enable_transcoder()
537 old_crtc_state->dsc.compression_enable) in intel_disable_transcoder()
1952 if (crtc_state->dsc.compression_enable) in get_crtc_power_domains()
4651 crtc_state->dsc.compression_enabled_on_link = limits->link_dsc_pipes & BIT(crtc->pipe); in intel_modeset_pipe_config()
5436 PIPE_CONF_CHECK_BOOL(dsc.config.block_pred_enable); in intel_pipe_config_compare()
5437 PIPE_CONF_CHECK_BOOL(dsc.config.convert_rgb); in intel_pipe_config_compare()
5438 PIPE_CONF_CHECK_BOOL(dsc.config.simple_422); in intel_pipe_config_compare()
5439 PIPE_CONF_CHECK_BOOL(dsc.config.native_422); in intel_pipe_config_compare()
5440 PIPE_CONF_CHECK_BOOL(dsc.config.native_420); in intel_pipe_config_compare()
5441 PIPE_CONF_CHECK_BOOL(dsc.config.vbr_enable); in intel_pipe_config_compare()
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/linux/drivers/media/platform/samsung/s5p-mfc/
H A Ds5p_mfc_opr_v5.c40 ctx->dsc.size = buf_size->dsc; in s5p_mfc_alloc_dec_temp_buffers_v5()
41 ret = s5p_mfc_alloc_priv_buf(dev, BANK_L_CTX, &ctx->dsc); in s5p_mfc_alloc_dec_temp_buffers_v5()
47 BUG_ON(ctx->dsc.dma & ((1 << MFC_BANK1_ALIGN_ORDER) - 1)); in s5p_mfc_alloc_dec_temp_buffers_v5()
48 memset(ctx->dsc.virt, 0, ctx->dsc.size); in s5p_mfc_alloc_dec_temp_buffers_v5()
57 s5p_mfc_release_priv_buf(ctx->dev, &ctx->dsc); in s5p_mfc_release_dec_desc_buffer_v5()
350 mfc_write(dev, OFFSETA(ctx->dsc.dma), S5P_FIMV_SI_CH0_DESC_ADR); in s5p_mfc_set_dec_desc_buffer()
351 mfc_write(dev, buf_size->dsc, S5P_FIMV_SI_CH0_DESC_SIZE); in s5p_mfc_set_dec_desc_buffer()
/linux/drivers/gpu/drm/amd/display/dc/hwss/
H A Dhw_sequencer.h227 struct display_stream_compressor *dsc; member
233 struct display_stream_compressor *dsc; member
244 struct display_stream_compressor *dsc; member
248 struct display_stream_compressor *dsc; member
615 struct display_stream_compressor *dsc; member
620 struct display_stream_compressor *dsc; member
1729 struct display_stream_compressor *dsc);
1841 struct display_stream_compressor *dsc,
1845 struct display_stream_compressor *dsc,
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c1546 if (otg_master->stream_res.dsc) in update_dsc_for_odm_change()
1549 if (old_otg_master && old_otg_master->stream_res.dsc) { in update_dsc_for_odm_change()
1553 if (old_pipe->stream_res.dsc && !new_pipe->stream_res.dsc) in update_dsc_for_odm_change()
1554 old_pipe->stream_res.dsc->funcs->dsc_disconnect( in update_dsc_for_odm_change()
1555 old_pipe->stream_res.dsc); in update_dsc_for_odm_change()
1626 if (otg_master->stream_res.dsc && otg_master->stream->timing.flags.DSC) { in dcn401_add_dsc_sequence_for_odm_change()
1643 otg_master->stream_res.dsc->inst, num_slices_h); in dcn401_add_dsc_sequence_for_odm_change()
1655 if (!odm_pipe->stream_res.dsc) in dcn401_add_dsc_sequence_for_odm_change()
1661 odm_pipe->stream_res.dsc->inst, num_slices_h); in dcn401_add_dsc_sequence_for_odm_change()
1675 } else if (otg_master->stream_res.dsc && !otg_master->stream->timing.flags.DSC) { in dcn401_add_dsc_sequence_for_odm_change()
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/linux/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5_cfg.h109 struct mdp5_sub_block dsc; member

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