Searched refs:drm_fb (Results 1 – 2 of 2) sorted by relevance
201 struct drm_framebuffer *drm_fb; in intel_dpt_resume() local207 drm_for_each_fb(drm_fb, display->drm) { in intel_dpt_resume()208 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb); in intel_dpt_resume()228 struct drm_framebuffer *drm_fb; in intel_dpt_suspend() local235 drm_for_each_fb(drm_fb, display->drm) { in intel_dpt_suspend()236 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb); in intel_dpt_suspend()
847 struct drm_framebuffer *drm_fb; in nv04_crtc_do_mode_set_base() local858 drm_fb = crtc->primary->fb; in nv04_crtc_do_mode_set_base()860 nvbo = nouveau_gem_object(drm_fb->obj[0]); in nv04_crtc_do_mode_set_base()863 if (nv_crtc->lut.depth != drm_fb->format->depth) { in nv04_crtc_do_mode_set_base()864 nv_crtc->lut.depth = drm_fb->format->depth; in nv04_crtc_do_mode_set_base()870 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (drm_fb->format->depth + 1) / 8; in nv04_crtc_do_mode_set_base()872 if (drm_fb->format->depth == 16) in nv04_crtc_do_mode_set_base()878 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = drm_fb->pitches[0] >> 3; in nv04_crtc_do_mode_set_base()880 XLATE(drm_fb->pitches[0] >> 3, 8, NV_CIO_CRE_RPC0_OFFSET_10_8); in nv04_crtc_do_mode_set_base()882 XLATE(drm_fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11); in nv04_crtc_do_mode_set_base()[all …]