Home
last modified time | relevance | path

Searched refs:drm_dp_dpcd_writeb (Results 1 – 17 of 17) sorted by relevance

/linux/drivers/gpu/drm/bridge/analogix/
H A Danalogix_dp_core.c125 ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en); in analogix_dp_enable_sink_psr()
133 ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en); in analogix_dp_enable_sink_psr()
141 ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en); in analogix_dp_enable_sink_psr()
170 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, in analogix_dp_enable_rx_to_enhanced_mode()
174 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, in analogix_dp_enable_rx_to_enhanced_mode()
221 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, in analogix_dp_training_pattern_dis()
278 retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, in analogix_dp_link_start()
405 retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, in analogix_dp_process_clock_recovery()
770 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, in analogix_dp_enable_scramble()
779 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, in analogix_dp_enable_scramble()
[all …]
/linux/drivers/gpu/drm/xlnx/
H A Dzynqmp_dp.c772 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, in zynqmp_dp_link_train_cr()
842 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, in zynqmp_dp_link_train_ce()
895 drm_dp_dpcd_writeb(&dp->aux, DP_DOWNSPREAD_CTRL, in zynqmp_dp_setup()
899 drm_dp_dpcd_writeb(&dp->aux, DP_DOWNSPREAD_CTRL, 0); in zynqmp_dp_setup()
902 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, aux_lane_cnt); in zynqmp_dp_setup()
908 ret = drm_dp_dpcd_writeb(&dp->aux, DP_MAIN_LINK_CHANNEL_CODING_SET, in zynqmp_dp_setup()
915 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LINK_BW_SET, bw_code); in zynqmp_dp_setup()
966 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, in zynqmp_dp_train()
1610 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, in zynqmp_dp_bridge_atomic_enable()
1639 drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, DP_SET_POWER_D3); in zynqmp_dp_bridge_atomic_disable()
[all …]
/linux/drivers/gpu/drm/mediatek/
H A Dmtk_dp.c1378 drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); in mtk_dp_aux_panel_poweron()
1382 drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, DP_SET_POWER_D3); in mtk_dp_aux_panel_poweron()
1562 drm_dp_dpcd_writeb(&mtk_dp->aux, DP_TRAINING_LANE0_SET + lane, in mtk_dp_train_update_swing_pre()
1595 drm_dp_dpcd_writeb(&mtk_dp->aux, DP_TRAINING_PATTERN_SET, aux_offset); in mtk_dp_pattern()
1603 drm_dp_dpcd_writeb(&mtk_dp->aux, DP_LINK_BW_SET, target_link_rate); in mtk_dp_train_setting()
1604 drm_dp_dpcd_writeb(&mtk_dp->aux, DP_LANE_COUNT_SET, in mtk_dp_train_setting()
1608 drm_dp_dpcd_writeb(&mtk_dp->aux, DP_DOWNSPREAD_CTRL, in mtk_dp_train_setting()
1687 drm_dp_dpcd_writeb(&mtk_dp->aux, DP_TRAINING_PATTERN_SET, in mtk_dp_train_cr()
1723 drm_dp_dpcd_writeb(&mtk_dp->aux, DP_TRAINING_PATTERN_SET, in mtk_dp_train_eq()
1732 drm_dp_dpcd_writeb(&mtk_dp->aux, DP_TRAINING_PATTERN_SET, in mtk_dp_train_eq()
[all …]
/linux/drivers/gpu/drm/msm/dp/
H A Ddp_link.c70 len = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value); in msm_dp_aux_link_power_up()
95 err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value); in msm_dp_aux_link_power_down()
781 ret = drm_dp_dpcd_writeb(link->aux, DP_TEST_RESPONSE, in msm_dp_link_send_test_response()
826 ret = drm_dp_dpcd_writeb(link->aux, DP_TEST_EDID_CHECKSUM, in msm_dp_link_send_edid_checksum()
H A Ddp_ctrl.c186 err = drm_dp_dpcd_writeb(aux, DP_LANE_COUNT_SET, lane_count); in msm_dp_aux_link_configure()
192 err = drm_dp_dpcd_writeb(aux, DP_LINK_RATE_SET, link->rate_set); in msm_dp_aux_link_configure()
196 err = drm_dp_dpcd_writeb(aux, DP_LINK_BW_SET, bw_code); in msm_dp_aux_link_configure()
1393 ret = drm_dp_dpcd_writeb(ctrl->aux, reg, buf); in msm_dp_ctrl_train_pattern_set()
/linux/drivers/gpu/drm/i915/display/
H A Dintel_alpm.c437 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, val); in intel_alpm_enable_sink()
582 drm_dp_dpcd_writeb(aux, DP_RECEIVER_ALPM_STATUS, val); in intel_alpm_get_error()
H A Dintel_psr.c794 drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, val); in _panel_replay_enable_sink()
796 drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG2, in _panel_replay_enable_sink()
824 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val); in _psr_enable_sink()
827 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val); in _psr_enable_sink()
840 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); in intel_psr_enable_sink()
851 drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, in intel_psr_panel_replay_enable_sink()
2354 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); in intel_psr_disable_locked()
2357 drm_dp_dpcd_writeb(&intel_dp->aux, in intel_psr_disable_locked()
3451 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); in intel_psr_handle_irq()
3805 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val); in psr_capability_changed_check()
[all …]
H A Dintel_dp.c3567 return drm_dp_dpcd_writeb(aux, DP_DSC_ENABLE, val); in write_dsc_decompression_flag()
3792 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode); in intel_dp_set_power()
3806 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode); in intel_dp_set_power()
4078 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); in intel_dp_pcon_set_tmds_mode()
4084 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); in intel_dp_pcon_set_tmds_mode()
4236 if (drm_dp_dpcd_writeb(&intel_dp->aux, in intel_dp_configure_protocol_converter()
4272 if (drm_dp_dpcd_writeb(&intel_dp->aux, in intel_dp_configure_protocol_converter()
5421 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0) in intel_dp_handle_hdmi_link_status_change()
5665 drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val); in intel_dp_check_device_service_irq()
5695 if (drm_dp_dpcd_writeb(&intel_dp->aux, in intel_dp_check_link_service_irq()
H A Dintel_dp_aux_backlight.c341 drm_dp_dpcd_writeb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, ctrl) != 1) in intel_dp_aux_hdr_enable_backlight()
/linux/drivers/gpu/drm/bridge/cadence/
H A Dcdns-mhdp8546-core.c812 drm_dp_dpcd_writeb(&mhdp->aux, DP_TRAINING_PATTERN_SET, in cdns_mhdp_link_training_init()
852 drm_dp_dpcd_writeb(&mhdp->aux, DP_TRAINING_PATTERN_SET, in cdns_mhdp_link_training_init()
993 drm_dp_dpcd_writeb(&mhdp->aux, DP_TRAINING_PATTERN_SET, in cdns_mhdp_link_training_channel_eq()
1251 drm_dp_dpcd_writeb(&mhdp->aux, DP_TRAINING_PATTERN_SET, in cdns_mhdp_link_training()
1282 drm_dp_dpcd_writeb(&mhdp->aux, DP_TRAINING_PATTERN_SET, in cdns_mhdp_link_training()
/linux/include/drm/display/
H A Ddrm_dp_helper.h658 static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux, in drm_dp_dpcd_writeb() function
/linux/drivers/gpu/drm/bridge/
H A Dtc358767.c1174 ret = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, tmp[0]); in tc_main_link_enable()
1311 ret = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, tmp[0]); in tc_main_link_enable()
H A Dti-sn65dsi86.c1137 drm_dp_dpcd_writeb(&pdata->aux, DP_EDP_CONFIGURATION_SET, in ti_sn_bridge_atomic_enable()
/linux/drivers/gpu/drm/nouveau/dispnv50/
H A Ddisp.c1408 rc = drm_dp_dpcd_writeb(aux, DP_SINK_COUNT_ESI + 1, ack[1]); in nv50_mstm_service()
1447 ret = drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0); in nv50_mstm_detect()
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_mst_types.c792 wret = drm_dp_dpcd_writeb(&aconnector->dm_dp_aux.aux, in dm_handle_mst_sideband_msg_ready_event()
H A Damdgpu_dm.c2779 ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL, in resume_mst_branch_status()
/linux/drivers/gpu/drm/bridge/synopsys/
H A Ddw-dp.c720 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, in dw_dp_link_train_set_pattern()