Searched refs:dram_timings (Results 1 – 2 of 2) sorted by relevance
364 u32 tFC_lpddr4 = 1000 * next->dram_timings[T_FC_LPDDR4]; in tegra210_emc_r21021_set_clock()668 tRTM = fake->dram_timings[RL] + div_o3(3600, src_clk_period) + in tegra210_emc_r21021_set_clock()1056 value = (1000 * fake->dram_timings[T_RP]) / src_clk_period; in tegra210_emc_r21021_set_clock()1065 delay += (1000 * fake->dram_timings[T_RP]) / in tegra210_emc_r21021_set_clock()1067 delay += 4000 * fake->dram_timings[T_RFC]; in tegra210_emc_r21021_set_clock()1089 delay = ((1000 * fake->dram_timings[T_RP] / src_clk_period) + in tegra210_emc_r21021_set_clock()1090 (1000 * fake->dram_timings[T_RFC] / src_clk_period)); in tegra210_emc_r21021_set_clock()1158 div_o3(1000 * next->dram_timings[T_PDEX], in tegra210_emc_r21021_set_clock()1166 next->dram_timings[T_PDEX]); in tegra210_emc_r21021_set_clock()1171 delay = div_o3(1000 * next->dram_timings[T_PDEX], in tegra210_emc_r21021_set_clock()
843 u32 dram_timings[DRAM_TIMINGS_NUM]; member