Searched refs:dram_bw_table (Results 1 – 3 of 3) sorted by relevance
10 …onst struct dml2_dram_params *dram_config, struct dml2_mcg_dram_bw_to_min_clk_table *dram_bw_table) in dram_bw_kbps_to_uclk_khz() argument22 for (i = 0; i < dram_bw_table->num_entries; i++) in dram_bw_kbps_to_uclk_khz()23 if (dram_bw_table->entries[i].pre_derate_dram_bw_kbps >= bandwidth_kbps) { in dram_bw_kbps_to_uclk_khz()24 uclk_khz = dram_bw_table->entries[i].min_uclk_khz; in dram_bw_kbps_to_uclk_khz()44 *dcfclk = in_out->min_clk_table->dram_bw_table.entries[min_clock_index_for_latency].min_dcfclk_khz; in get_minimum_clocks_for_latency()45 *fclk = in_out->min_clk_table->dram_bw_table.entries[min_clock_index_for_latency].min_fclk_khz; in get_minimum_clocks_for_latency()46 …*uclk = dram_bw_kbps_to_uclk_khz(in_out->min_clk_table->dram_bw_table.entries[min_clock_index_for_… in get_minimum_clocks_for_latency()47 &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); in get_minimum_clocks_for_latency()68 &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); in calculate_system_active_minimums()73 &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); in calculate_system_active_minimums()[all …]
15 …out->stage1.min_clk_index_for_latency = dml->min_clk_table.dram_bw_table.num_entries - 1; //dml->m… in setup_unoptimized_display_config_with_meta()1166 pmo_init_params.mcg_clock_table_size = dml->min_clk_table.dram_bw_table.num_entries; in dml2_top_soc15_initialize_instance()
7101 …truct dml2_dram_params *dram_config, const struct dml2_mcg_dram_bw_to_min_clk_table *dram_bw_table) in uclk_khz_to_dram_bw_mbps() argument7109 for (i = 0; i < dram_bw_table->num_entries; i++) in uclk_khz_to_dram_bw_mbps()7110 if (dram_bw_table->entries[i].min_uclk_khz >= uclk_khz) { in uclk_khz_to_dram_bw_mbps()7111 bw_mbps = (double)dram_bw_table->entries[i].pre_derate_dram_bw_kbps / 1000.0; in uclk_khz_to_dram_bw_mbps()7991 …mode_lib->ms.DCFCLK = ((double)min_clk_table->dram_bw_table.entries[in_out_params->min_clk_index].… in dml_core_mode_support()7992 …mode_lib->ms.FabricClock = ((double)min_clk_table->dram_bw_table.entries[in_out_params->min_clk_in… in dml_core_mode_support()7998 …mode_lib->ms.uclk_freq_mhz = (double)min_clk_table->dram_bw_table.entries[in_out_params->min_clk_i… in dml_core_mode_support()8000 …mode_lib->ms.uclk_freq_mhz = dram_bw_kbps_to_uclk_mhz(min_clk_table->dram_bw_table.entries[in_out_… in dml_core_mode_support()8001 …mode_lib->ms.dram_bw_mbps = ((double)min_clk_table->dram_bw_table.entries[in_out_params->min_clk_i… in dml_core_mode_support()8002 …lib->ms.max_dram_bw_mbps = ((double)min_clk_table->dram_bw_table.entries[min_clk_table->dram_bw_ta… in dml_core_mode_support()[all …]