Searched refs:dprefclk_khz (Results 1 – 11 of 11) sorted by relevance
200 clk_mgr->base.dprefclk_khz = REG_READ(CLK4_CLK2_CURRENT_CNT); in dcn201_clk_mgr_construct()201 clk_mgr->base.dprefclk_khz *= 100; in dcn201_clk_mgr_construct()203 if (clk_mgr->base.dprefclk_khz == 0) in dcn201_clk_mgr_construct()204 clk_mgr->base.dprefclk_khz = 600000; in dcn201_clk_mgr_construct()
136 clk_mgr->base.dprefclk_khz = 600000; in dce120_clk_mgr_construct()143 clk_mgr->base.dprefclk_khz = 625000; in dce121_clk_mgr_construct()
164 DC_LOG_DEBUG("%s %d\n", __func__, clk_mgr->base.dprefclk_khz / 1000); in dcn301_smu_set_dprefclk()169 khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz)); in dcn301_smu_set_dprefclk()
196 return clk_mgr->base.dprefclk_khz; in dcn314_smu_set_dprefclk()201 khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz)); in dcn314_smu_set_dprefclk()
177 return clk_mgr->base.dprefclk_khz; in dcn31_smu_set_dprefclk()182 khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz)); in dcn31_smu_set_dprefclk()
274 uint32_t dprefclk_khz; member352 …int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where th… member
178 return clk_mgr_adjust_dp_ref_freq_for_ss(clk_mgr_dce, clk_mgr_dce->dprefclk_khz); in dce12_get_dp_ref_freq_khz()934 clk_mgr_dce->dprefclk_khz = 600000; in dce120_clk_mgr_create()955 clk_mgr_dce->dprefclk_khz = 625000; in dce121_clk_mgr_create()
542 clk_mgr->base.dprefclk_khz = 730000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved in dcn3_clk_mgr_construct()556 clk_mgr->base.dprefclk_khz = s.dprefclk * 1000; in dcn3_clk_mgr_construct()
553 clk_mgr->base.dprefclk_khz = 700000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved in dcn20_clk_mgr_construct()581 clk_mgr->base.dprefclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR in dcn20_clk_mgr_construct()
331 clk_mgr->base.dprefclk_khz = 600000; in rv1_clk_mgr_construct()
765 clk_mgr->base.dprefclk_khz = 600000; in rn_clk_mgr_construct()