Searched refs:dppclk (Results 1 – 15 of 15) sorted by relevance
128 struct dml2_clk_table dppclk; member
33 unsigned int dppclk; member43 unsigned int dppclk; member
189 uint32_t dppclk; member
1223 v->dppclk = v->dispclk / v->dispclk_dppclk_ratio; in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()1300 …>display_pipe_line_delivery_time_luma[k] = v->swath_width_y[k] / v->pscl_throughput[k] / v->dppclk; in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()1312 …ine_delivery_time_chroma[k] = v->swath_width_y[k] / 2.0 / v->pscl_throughput_chroma[k] / v->dppclk; in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()1423 …=dcn_bw_floor2(v->lines_in_dety[k] +dcn_bw_min2(v->lines_in_dety[k] * v->dppclk * v->byte_per_pixe… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()1426 …=dcn_bw_floor2(v->lines_in_detc[k] +dcn_bw_min2(v->lines_in_detc[k] * v->dppclk * v->byte_per_pixe… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()1643 …v->dstx_after_scaler = 90.0 * v->pixel_clock[k] / v->dppclk + 42.0 * v->pixel_clock[k] / v->dispcl… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()1654 …v->total_repeater_delay_time = v->max_inter_dcn_tile_repeaters * (2.0 / v->dppclk + 3.0 / v->dispc… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()1655 …v->v_update_width_pix[k] = (14.0 / v->dcf_clk_deep_sleep + 12.0 / v->dppclk + v->total_repeater_de… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()1656 …_pix[k] = dcn_bw_max2(150.0 / v->dppclk, v->total_repeater_delay_time + 20.0 / v->dcf_clk_deep_sle… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()1786 …pipe_line_delivery_time_luma_prefetch[k] = v->swath_width_y[k] / v->pscl_throughput[k] / v->dppclk; in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()[all …]
496 input->clks_cfg.dppclk_mhz = v->dppclk; in dcn_bw_calc_rq_dlg_ttu()
367 regs_and_bypass->dppclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR in dcn401_dump_clk_registers()509 clk_register_dump.dppclk, in dcn401_auto_dpm_test_log()1108 clk_mgr_base->clks.dppclk_khz = clk_mgr_base->boot_snapshot.dppclk; in dcn401_build_update_display_clocks_sequence()1515 clk_mgr->base.boot_snapshot.dppclk; in dcn401_get_max_clock_khz()
412 uint32_t dppclk : 1; member
413 …_to_next_dpm(&display_cfg->plane_programming[i].min_clocks.dcn4x.dppclk_khz, &state_table->dppclk); in map_min_clocks_to_dpm()426 result = round_up_to_next_dpm(&display_cfg->min_clocks.dcn4x.dpprefclk_khz, &state_table->dppclk); in map_min_clocks_to_dpm()
320 regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10; in rn_dump_clk_registers()
632 regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10; in dcn35_save_clk_registers()1312 clk_mgr->base.boot_snapshot.dppclk; in dcn35_get_max_clock_khz()
1511 new_pipe->update_flags.bits.dppclk = 1; in dcn20_detect_pipe_changes()1591 new_pipe->update_flags.bits.dppclk = 1; in dcn20_detect_pipe_changes()1677 if (pipe_ctx->update_flags.bits.dppclk) in dcn20_update_dchubp_dpp()
916 regs_and_bypass->dppclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR in dcn32_dump_clk_registers()
2792 new_pipe->update_flags.bits.dppclk = 1; in dcn401_detect_pipe_changes()2871 new_pipe->update_flags.bits.dppclk = 1; in dcn401_detect_pipe_changes()3597 if (pipe_ctx->update_flags.bits.dppclk) in dcn401_update_dchubp_dpp_sequence()
1475 phantom_pipe->update_flags.bits.dppclk = 1; in dcn32_apply_update_flags_for_phantom()
7977 mode_lib->ms.max_dppclk_freq_mhz = (double)min_clk_table->max_ss_clocks_khz.dppclk / 1000; in dml_core_mode_support()