| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn35/ |
| H A D | dcn35_dccg.c | 1131 uint32_t dpp_inst, uint32_t enable) in dcn35_set_dppclk_enable() argument
1136 switch (dpp_inst) { in dcn35_set_dppclk_enable()
1152 DC_LOG_DEBUG("%s: dpp_inst(%d) DPPCLK_EN = %d\n", __func__, dpp_inst, enable); in dcn35_set_dppclk_enable()
1156 void dccg35_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg35_update_dpp_dto() argument
1160 if (dccg->dpp_clock_gated[dpp_inst]) { in dccg35_update_dpp_dto()
1179 dccg35_set_dppclk_rcg(dccg, dpp_inst, false); in dccg35_update_dpp_dto()
1181 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, in dccg35_update_dpp_dto()
1185 dcn35_set_dppclk_enable(dccg, dpp_inst, true); in dccg35_update_dpp_dto()
1187 dcn35_set_dppclk_enable(dccg, dpp_inst, false); in dccg35_update_dpp_dto()
1188 dccg35_set_dppclk_rcg(dccg, dpp_inst, true); in dccg35_update_dpp_dto()
[all …]
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| H A D | dcn35_dccg.h | 254 void dccg35_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk);
263 void dccg35_dpp_root_clock_control(struct dccg *dccg, unsigned int dpp_inst, bool clock_on);
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn21/ |
| H A D | dcn21_dccg.c | 46 static void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg21_update_dpp_dto() argument
88 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, in dccg21_update_dpp_dto()
93 DPPCLK_DTO_ENABLE[dpp_inst], 1); in dccg21_update_dpp_dto()
96 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; in dccg21_update_dpp_dto()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn20/ |
| H A D | dcn20_dccg.c | 47 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg2_update_dpp_dto() argument
64 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, in dccg2_update_dpp_dto()
68 DPPCLK_DTO_ENABLE[dpp_inst], 1); in dccg2_update_dpp_dto()
71 DPPCLK_DTO_ENABLE[dpp_inst], 0); in dccg2_update_dpp_dto()
74 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; in dccg2_update_dpp_dto()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn314/ |
| H A D | dcn314_dccg.c | 332 unsigned int dpp_inst, in dccg314_dpp_root_clock_control() argument
337 if (dccg->dpp_clock_gated[dpp_inst] != clock_on) in dccg314_dpp_root_clock_control()
342 REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_ENABLE[dpp_inst], 0); in dccg314_dpp_root_clock_control()
343 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, in dccg314_dpp_root_clock_control()
348 REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_ENABLE[dpp_inst], 1); in dccg314_dpp_root_clock_control()
349 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, in dccg314_dpp_root_clock_control()
354 dccg->dpp_clock_gated[dpp_inst] = !clock_on; in dccg314_dpp_root_clock_control()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn314/ |
| H A D | dcn314_hwseq.h | 46 void dcn314_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on);
50 void dcn314_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on);
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn401/ |
| H A D | dcn401_dccg.c | 57 uint32_t dpp_inst, uint32_t enable) in dcn401_set_dppclk_enable() argument
61 switch (dpp_inst) { in dcn401_set_dppclk_enable()
78 void dccg401_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg401_update_dpp_dto() argument
95 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, in dccg401_update_dpp_dto()
98 dcn401_set_dppclk_enable(dccg, dpp_inst, true); in dccg401_update_dpp_dto()
100 dcn401_set_dppclk_enable(dccg, dpp_inst, false); in dccg401_update_dpp_dto()
103 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; in dccg401_update_dpp_dto()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn302/ |
| H A D | dcn302_hwseq.c | 45 void dcn302_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on) in dcn302_dpp_pg_control() argument
55 switch (dpp_inst) { in dcn302_dpp_pg_control()
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| H A D | dcn302_hwseq.h | 31 void dcn302_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on);
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn31/ |
| H A D | dcn31_dccg.c | 47 void dccg31_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg31_update_dpp_dto() argument
51 if (dccg->dpp_clock_gated[dpp_inst]) { in dccg31_update_dpp_dto()
72 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, in dccg31_update_dpp_dto()
76 DPPCLK_DTO_ENABLE[dpp_inst], 1); in dccg31_update_dpp_dto()
79 DPPCLK_DTO_ENABLE[dpp_inst], 0); in dccg31_update_dpp_dto()
81 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; in dccg31_update_dpp_dto()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn303/ |
| H A D | dcn303_hwseq.h | 32 void dcn303_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on);
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| H A D | dcn303_hwseq.c | 46 void dcn303_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on) in dcn303_dpp_pg_control() argument
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| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | dccg.h | 215 int dpp_inst,
317 unsigned int dpp_inst,
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| H A D | hw_shared.h | 90 int dpp_inst; member
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn201/ |
| H A D | dcn201_dccg.c | 48 static void dccg201_update_dpp_dto(struct dccg *dccg, int dpp_inst, in dccg201_update_dpp_dto() argument
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| H A D | rn_clk_mgr.c | 114 int dpp_inst, dppclk_khz, prev_dppclk_khz; in rn_update_clocks_update_dpp_dto() local
119 dpp_inst = clk_mgr->base.ctx->dc->res_pool->dpps[i]->inst; in rn_update_clocks_update_dpp_dto()
122 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[dpp_inst]; in rn_update_clocks_update_dpp_dto()
126 clk_mgr->dccg, dpp_inst, dppclk_khz); in rn_update_clocks_update_dpp_dto()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| H A D | dcn20_clk_mgr.c | 111 int dpp_inst, dppclk_khz, prev_dppclk_khz; in dcn20_update_clocks_update_dpp_dto() local
116 dpp_inst = i; in dcn20_update_clocks_update_dpp_dto()
123 clk_mgr->dccg, dpp_inst, dppclk_khz); in dcn20_update_clocks_update_dpp_dto()
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_hw_sequencer.c | 2888 unsigned int dpp_inst = params->dpp_pg_control_params.dpp_inst; in hwss_dpp_pg_control() local
2892 hws->funcs.dpp_pg_control(hws, dpp_inst, power_on); in hwss_dpp_pg_control()
2924 unsigned int dpp_inst = params->dpp_root_clock_control_params.dpp_inst; in hwss_dpp_root_clock_control() local
2928 hws->funcs.dpp_root_clock_control(hws, dpp_inst, clock_on); in hwss_dpp_root_clock_control()
2944 int dpp_inst = params->dccg_update_dpp_dto_params.dpp_inst; in hwss_dccg_update_dpp_dto() local
2948 dccg->funcs->update_dpp_dto(dccg, dpp_inst, dppclk_khz); in hwss_dccg_update_dpp_dto()
3671 unsigned int dpp_inst, in hwss_add_dpp_root_clock_control() argument
3677 seq_state->steps[*seq_state->num_steps].params.dpp_root_clock_control_params.dpp_inst = dpp_inst; in hwss_add_dpp_root_clock_control()
3685 unsigned int dpp_inst, in hwss_add_dpp_pg_control() argument
3691 seq_state->steps[*seq_state->num_steps].params.dpp_pg_control_params.dpp_inst = dpp_inst; in hwss_add_dpp_pg_control()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/ |
| H A D | hw_sequencer.h | 579 unsigned int dpp_inst; member
599 unsigned int dpp_inst; member
632 int dpp_inst; member
1868 unsigned int dpp_inst,
1873 unsigned int dpp_inst,
1909 int dpp_inst,
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| /linux/drivers/gpu/drm/amd/display/dc/link/protocols/ |
| H A D | link_dp_panel_replay.c | 309 cmd.pr_copy_settings.data.dpp_inst = pipe_ctx->plane_res.dpp->inst; in dp_pr_copy_settings()
311 cmd.pr_copy_settings.data.dpp_inst = 0; in dp_pr_copy_settings()
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| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dmub_replay.c | 154 copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst; in dmub_replay_copy_settings()
156 copy_settings_data->dpp_inst = 0; in dmub_replay_copy_settings()
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| H A D | dmub_psr.c | 344 copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst; in dmub_psr_copy_settings()
346 copy_settings_data->dpp_inst = 0; in dmub_psr_copy_settings()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| H A D | dcn20_hwseq.h | 104 unsigned int dpp_inst,
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.c | 321 int dpp_inst = 0, dppclk_khz, prev_dppclk_khz; in dcn32_update_clocks_update_dpp_dto() local
326 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst; in dcn32_update_clocks_update_dpp_dto()
344 clk_mgr->dccg, dpp_inst, dppclk_khz); in dcn32_update_clocks_update_dpp_dto()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_clk_mgr.c | 289 int dpp_inst = 0, dppclk_khz, prev_dppclk_khz; in dcn35_update_clocks_update_dpp_dto() local
294 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst; in dcn35_update_clocks_update_dpp_dto()
312 clk_mgr->dccg, dpp_inst, dppclk_khz); in dcn35_update_clocks_update_dpp_dto()
313 dppclk_active[dpp_inst] = true; in dcn35_update_clocks_update_dpp_dto()
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