Searched refs:dpp_inst (Results 1 – 8 of 8) sorted by relevance
| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn21/ |
| H A D | dcn21_dccg.c | 46 static void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg21_update_dpp_dto() argument
88 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, in dccg21_update_dpp_dto()
93 DPPCLK_DTO_ENABLE[dpp_inst], 1); in dccg21_update_dpp_dto()
96 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; in dccg21_update_dpp_dto()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn20/ |
| H A D | dcn20_dccg.c | 47 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg2_update_dpp_dto() argument
64 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, in dccg2_update_dpp_dto()
68 DPPCLK_DTO_ENABLE[dpp_inst], 1); in dccg2_update_dpp_dto()
71 DPPCLK_DTO_ENABLE[dpp_inst], 0); in dccg2_update_dpp_dto()
74 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; in dccg2_update_dpp_dto()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn314/ |
| H A D | dcn314_hwseq.h | 46 void dcn314_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on);
50 void dcn314_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on);
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn302/ |
| H A D | dcn302_hwseq.c | 45 void dcn302_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on) in dcn302_dpp_pg_control() argument
55 switch (dpp_inst) { in dcn302_dpp_pg_control()
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| H A D | dcn302_hwseq.h | 31 void dcn302_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on);
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn303/ |
| H A D | dcn303_hwseq.h | 32 void dcn303_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on);
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn201/ |
| H A D | dcn201_dccg.c | 48 static void dccg201_update_dpp_dto(struct dccg *dccg, int dpp_inst, in dccg201_update_dpp_dto() argument
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_clk_mgr.c | 303 int dpp_inst = 0, dppclk_khz, prev_dppclk_khz; in dcn35_update_clocks_update_dpp_dto() local
308 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst; in dcn35_update_clocks_update_dpp_dto()
326 clk_mgr->dccg, dpp_inst, dppclk_khz); in dcn35_update_clocks_update_dpp_dto()
327 dppclk_active[dpp_inst] = true; in dcn35_update_clocks_update_dpp_dto()
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