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Searched refs:dpp_base (Results 1 – 18 of 18) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn30/
H A Ddcn30_dpp.c44 void dpp30_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s) in dpp30_read_state() argument
46 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp30_read_state()
89 struct dpp *dpp_base, in dpp3_program_post_csc() argument
94 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_program_post_csc()
162 void dpp3_set_pre_degam(struct dpp *dpp_base, enum dc_transfer_func_predefined tr) in dpp3_set_pre_degam() argument
164 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_set_pre_degam()
205 struct dpp *dpp_base, in dpp3_cnv_setup() argument
212 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_cnv_setup()
368 dpp3_program_post_csc(dpp_base, color_space, select, in dpp3_cnv_setup()
371 dpp3_program_post_csc(dpp_base, color_space, select, NULL); in dpp3_cnv_setup()
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H A Ddcn30_dpp_cm.c44 struct dpp *dpp_base) in dpp3_enable_cm_block() argument
46 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_enable_cm_block()
51 if (dpp_base->ctx->dc->debug.cm_in_bypass) in dpp3_enable_cm_block()
57 static enum dc_lut_mode dpp30_get_gamcor_current(struct dpp *dpp_base) in dpp30_get_gamcor_current() argument
62 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp30_get_gamcor_current()
78 struct dpp *dpp_base, in dpp3_program_gammcor_lut() argument
84 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_program_gammcor_lut()
127 struct dpp *dpp_base, in dpp3_power_on_gamcor_lut() argument
130 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_power_on_gamcor_lut()
132 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) { in dpp3_power_on_gamcor_lut()
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/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn20/
H A Ddcn20_dpp_cm.c51 struct dpp *dpp_base) in dpp2_enable_cm_block() argument
53 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_enable_cm_block()
57 if (dpp_base->ctx->dc->debug.cm_in_bypass) in dpp2_enable_cm_block()
65 struct dpp *dpp_base, in dpp2_degamma_ram_inuse() argument
70 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_degamma_ram_inuse()
86 struct dpp *dpp_base, in dpp2_program_degamma_lut() argument
93 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_program_degamma_lut()
117 struct dpp *dpp_base, in dpp2_set_degamma_pwl() argument
122 dpp1_power_on_degamma_lut(dpp_base, true); in dpp2_set_degamma_pwl()
123 dpp2_enable_cm_block(dpp_base); in dpp2_set_degamma_pwl()
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H A Ddcn20_dpp.c51 void dpp20_read_state(struct dpp *dpp_base, in dpp20_read_state() argument
54 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp20_read_state()
78 struct dpp *dpp_base, in dpp2_power_on_obuf() argument
81 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_power_on_obuf()
93 struct dpp *dpp_base, in dpp2_dummy_program_input_lut() argument
98 struct dpp *dpp_base, in dpp2_cnv_setup() argument
105 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_cnv_setup()
244 dpp2_program_input_csc(dpp_base, color_space, select, &tbl_entry); in dpp2_cnv_setup()
246 dpp2_program_input_csc(dpp_base, color_space, select, NULL); in dpp2_cnv_setup()
255 dpp2_power_on_obuf(dpp_base, true); in dpp2_cnv_setup()
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/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn10/
H A Ddcn10_dpp_cm.c161 struct dpp *dpp_base, in dpp1_cm_set_gamut_remap() argument
164 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_set_gamut_remap()
233 void dpp1_cm_get_gamut_remap(struct dpp *dpp_base, in dpp1_cm_get_gamut_remap() argument
236 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_get_gamut_remap()
308 struct dpp *dpp_base, in dpp1_cm_set_output_csc_default() argument
311 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_set_output_csc_default()
378 struct dpp *dpp_base, in dpp1_cm_set_output_csc_adjustment() argument
381 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_set_output_csc_adjustment()
386 void dpp1_cm_power_on_regamma_lut(struct dpp *dpp_base, in dpp1_cm_power_on_regamma_lut() argument
389 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_power_on_regamma_lut()
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H A Ddcn10_dpp.c94 void dpp_read_state(struct dpp *dpp_base, in dpp_read_state() argument
97 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp_read_state()
188 void dpp_reset(struct dpp *dpp_base) in dpp_reset() argument
190 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp_reset()
204 struct dpp *dpp_base, const struct pwl_params *params, enum opp_regamma mode) in dpp1_cm_set_regamma_pwl() argument
206 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_set_regamma_pwl()
224 dpp1_cm_power_on_regamma_lut(dpp_base, true); in dpp1_cm_set_regamma_pwl()
225 dpp1_cm_configure_regamma_lut(dpp_base, dpp->is_write_to_ram_a_safe); in dpp1_cm_set_regamma_pwl()
228 dpp1_cm_program_regamma_luta_settings(dpp_base, params); in dpp1_cm_set_regamma_pwl()
230 dpp1_cm_program_regamma_lutb_settings(dpp_base, params); in dpp1_cm_set_regamma_pwl()
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H A Ddcn10_dpp_dscl.c124 struct dpp *dpp_base, in dpp1_dscl_get_dscl_mode() argument
130 if (dpp_base->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) { in dpp1_dscl_get_dscl_mode()
158 struct dpp *dpp_base, in dpp1_power_on_dscl() argument
161 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_power_on_dscl()
613 void dpp1_dscl_set_scaler_manual_scale(struct dpp *dpp_base, in dpp1_dscl_set_scaler_manual_scale() argument
617 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_dscl_set_scaler_manual_scale()
619 dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale); in dpp1_dscl_set_scaler_manual_scale()
630 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.dscl) { in dpp1_dscl_set_scaler_manual_scale()
632 dpp1_power_on_dscl(dpp_base, true); in dpp1_dscl_set_scaler_manual_scale()
659 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.dscl) in dpp1_dscl_set_scaler_manual_scale()
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H A Ddcn10_dpp.h1383 struct dpp *dpp_base,
1387 struct dpp *dpp_base,
1394 struct dpp *dpp_base,
1409 struct dpp *dpp_base,
1413 struct dpp *dpp_base,
1417 struct dpp *dpp_base,
1421 struct dpp *dpp_base,
1427 struct dpp *dpp_base,
1431 struct dpp *dpp_base,
1437 struct dpp *dpp_base,
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/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Ddpp.h210 struct dpp *dpp_base, const struct pwl_params *params);
212 void (*dpp_set_pre_degam)(struct dpp *dpp_base,
215 void (*dpp_program_cm_dealpha)(struct dpp *dpp_base,
219 struct dpp *dpp_base,
282 struct dpp *dpp_base,
286 struct dpp *dpp_base,
289 void (*dpp_program_degamma_pwl)(struct dpp *dpp_base,
293 struct dpp *dpp_base,
300 void (*dpp_full_bypass)(struct dpp *dpp_base);
303 struct dpp *dpp_base,
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/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn401/
H A Ddcn401_dpp_cm.c91 void dpp401_full_bypass(struct dpp *dpp_base) in dpp401_full_bypass() argument
93 struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base); in dpp401_full_bypass()
116 struct dpp *dpp_base, in dpp401_set_cursor_attributes() argument
119 struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base); in dpp401_set_cursor_attributes()
142 dpp_base->att.cur0_ctl.bits.expansion_mode = 0; in dpp401_set_cursor_attributes()
143 dpp_base->att.cur0_ctl.bits.cur0_rom_en = cur_rom_en; in dpp401_set_cursor_attributes()
144 dpp_base->att.cur0_ctl.bits.mode = color_format; in dpp401_set_cursor_attributes()
148 struct dpp *dpp_base, in dpp401_set_cursor_position() argument
154 struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base); in dpp401_set_cursor_position()
159 dpp_base->pos.cur0_ctl.bits.cur0_enable = cur_en; in dpp401_set_cursor_position()
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H A Ddcn401_dpp_dscl.c126 struct dpp *dpp_base, in dpp401_dscl_get_dscl_mode() argument
132 if (dpp_base->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) { in dpp401_dscl_get_dscl_mode()
160 struct dpp *dpp_base, in dpp401_power_on_dscl() argument
163 struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base); in dpp401_power_on_dscl()
668 static void dpp401_dscl_program_easf_v(struct dpp *dpp_base, const struct scaler_data *scl_data) in dpp401_dscl_program_easf_v() argument
670 struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base); in dpp401_dscl_program_easf_v()
783 static void dpp401_dscl_program_easf_h(struct dpp *dpp_base, const struct scaler_data *scl_data) in dpp401_dscl_program_easf_h() argument
785 struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base); in dpp401_dscl_program_easf_h()
888 static void dpp401_dscl_program_easf(struct dpp *dpp_base, const struct scaler_data *scl_data) in dpp401_dscl_program_easf() argument
890 struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base); in dpp401_dscl_program_easf()
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H A Ddcn401_dpp.c45 void dpp401_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s) in dpp401_read_state() argument
47 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp401_read_state()
56 struct dpp *dpp_base, in dpp401_dpp_setup() argument
63 struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base); in dpp401_dpp_setup()
214 dpp3_program_post_csc(dpp_base, color_space, select, in dpp401_dpp_setup()
217 dpp3_program_post_csc(dpp_base, color_space, select, NULL); in dpp401_dpp_setup()
H A Ddcn401_dpp.h681 struct dpp *dpp_base,
684 void dpp401_full_bypass(struct dpp *dpp_base);
687 struct dpp *dpp_base,
695 struct dpp *dpp_base,
699 struct dpp *dpp_base,
706 struct dpp *dpp_base,
722 void dpp401_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s);
725 struct dpp *dpp_base,
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn35/
H A Ddcn35_dpp.c41 struct dpp *dpp_base, in dpp35_dppclk_control() argument
45 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp35_dppclk_control()
71 struct dpp *dpp_base, in dpp35_program_bias_and_scale_fcnv() argument
74 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp35_program_bias_and_scale_fcnv()
H A Ddcn35_dpp.h53 struct dpp *dpp_base,
64 void dpp35_program_bias_and_scale_fcnv(struct dpp *dpp_base,
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
H A Ddcn30_hwseq.c224 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_blend_lut() local
232 &plane_state->blend_tf, &dpp_base->regamma_params, false); in dcn30_set_blend_lut()
236 blend_lut = &dpp_base->regamma_params; in dcn30_set_blend_lut()
238 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut); in dcn30_set_blend_lut()
246 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_mpc_shaper_3dlut() local
261 &dpp_base->shaper_params, true); in dcn30_set_mpc_shaper_3dlut()
262 shaper_lut = &dpp_base->shaper_params; in dcn30_set_mpc_shaper_3dlut()
308 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_input_transfer_func() local
313 if (dpp_base == NULL || plane_state == NULL) in dcn30_set_input_transfer_func()
321 dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf); in dcn30_set_input_transfer_func()
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/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn201/
H A Ddcn201_dpp.c45 struct dpp *dpp_base, in dpp201_cnv_setup() argument
52 struct dcn201_dpp *dpp = TO_DCN201_DPP(dpp_base); in dpp201_cnv_setup()
177 dpp1_program_input_csc(dpp_base, color_space, select, NULL); in dpp201_cnv_setup()
185 dpp2_power_on_obuf(dpp_base, true); in dpp201_cnv_setup()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_hwseq.c1817 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn10_set_input_transfer_func() local
1821 if (dpp_base == NULL) in dcn10_set_input_transfer_func()
1826 if (!dpp_base->ctx->dc->debug.always_use_regamma in dcn10_set_input_transfer_func()
1829 dpp_base->funcs->dpp_program_input_lut(dpp_base, &plane_state->gamma_correction); in dcn10_set_input_transfer_func()
1834 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_sRGB); in dcn10_set_input_transfer_func()
1837 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_xvYCC); in dcn10_set_input_transfer_func()
1840 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS); in dcn10_set_input_transfer_func()
1843 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL); in dcn10_set_input_transfer_func()
1844 cm_helper_translate_curve_to_degamma_hw_format(tf, &dpp_base->degamma_params); in dcn10_set_input_transfer_func()
1845 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params); in dcn10_set_input_transfer_func()
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