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Searched refs:dpll_hw_state (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/i915/display/
H A Dintel_dpll_mgr.c69 const struct intel_dpll_hw_state *dpll_hw_state);
86 struct intel_dpll_hw_state *dpll_hw_state);
94 const struct intel_dpll_hw_state *dpll_hw_state);
113 const struct intel_dpll_hw_state *dpll_hw_state);
358 const struct intel_dpll_hw_state *dpll_hw_state, in intel_find_shared_dpll() argument
385 if (memcmp(dpll_hw_state, in intel_find_shared_dpll()
387 sizeof(*dpll_hw_state)) == 0) { in intel_find_shared_dpll()
436 const struct intel_dpll_hw_state *dpll_hw_state) in intel_reference_shared_dpll() argument
443 shared_dpll[pll->index].hw_state = *dpll_hw_state; in intel_reference_shared_dpll()
525 struct intel_dpll_hw_state *dpll_hw_state) in ibx_pch_dpll_get_hw_state() argument
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H A Dintel_dpll_mgr.h418 const struct intel_dpll_hw_state *dpll_hw_state);
421 struct intel_dpll_hw_state *dpll_hw_state);
432 const struct intel_dpll_hw_state *dpll_hw_state);
H A Dintel_dpll.c376 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in i9xx_pll_refclk()
389 struct intel_dpll_hw_state *dpll_hw_state) in i9xx_dpll_get_hw_state() argument
392 struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx; in i9xx_dpll_get_hw_state()
425 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in i9xx_crtc_clock_get()
519 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in vlv_crtc_clock_get()
547 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in chv_crtc_clock_get()
1079 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in i9xx_compute_dpll()
1148 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in i8xx_compute_dpll()
1233 crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); in mtl_crtc_compute_clock()
1351 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in ilk_compute_dpll()
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H A Dintel_dpll.h27 struct intel_dpll_hw_state *dpll_hw_state);
H A Dintel_pch_display.c534 &crtc_state->dpll_hw_state); in ilk_pch_get_config()
537 tmp = crtc_state->dpll_hw_state.i9xx.dpll; in ilk_pch_get_config()
H A Dintel_crtc_state_dump.c344 intel_dpll_dump_hw_state(i915, &p, &pipe_config->dpll_hw_state); in intel_crtc_state_dump()
H A Dintel_ddi.c4071 &crtc_state->dpll_hw_state); in intel_ddi_get_clock()
4077 intel_cx0pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.cx0pll); in mtl_ddi_get_config()
4079 if (crtc_state->dpll_hw_state.cx0pll.tbt_mode) in mtl_ddi_get_config()
4082 crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); in mtl_ddi_get_config()
4090 intel_mpllb_readout_hw_state(encoder, &crtc_state->dpll_hw_state.mpllb); in dg2_ddi_get_config()
4091 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->dpll_hw_state.mpllb); in dg2_ddi_get_config()
4184 &crtc_state->dpll_hw_state); in icl_ddi_tc_get_clock()
H A Dintel_display.c1463 new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state; in intel_encoders_update_prepare()
3218 i9xx_dpll_get_hw_state(crtc, &pipe_config->dpll_hw_state); in i9xx_get_pipe_config()
3221 tmp = pipe_config->dpll_hw_state.i9xx.dpll_md; in i9xx_get_pipe_config()
3227 tmp = pipe_config->dpll_hw_state.i9xx.dpll; in i9xx_get_pipe_config()
4899 saved_state->dpll_hw_state = crtc_state->dpll_hw_state; in intel_crtc_prepare_cleared_state()
5675 PIPE_CONF_CHECK_PLL(dpll_hw_state); in intel_pipe_config_compare()
5679 PIPE_CONF_CHECK_PLL_CX0(dpll_hw_state.cx0pll); in intel_pipe_config_compare()
H A Dintel_display_types.h1060 struct intel_dpll_hw_state dpll_hw_state; member