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Searched refs:dpcd_lane_settings (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_dp_training.c357 union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX]) in dp_hw_to_dpcd_lane_settings()
364 dpcd_lane_settings[lane].bits.VOLTAGE_SWING_SET = in dp_hw_to_dpcd_lane_settings()
366 dpcd_lane_settings[lane].bits.PRE_EMPHASIS_SET = in dp_hw_to_dpcd_lane_settings()
368 dpcd_lane_settings[lane].bits.MAX_SWING_REACHED = in dp_hw_to_dpcd_lane_settings()
371 dpcd_lane_settings[lane].bits.MAX_PRE_EMPHASIS_REACHED = in dp_hw_to_dpcd_lane_settings()
376 dpcd_lane_settings[lane].tx_ffe.PRESET_VALUE = in dp_hw_to_dpcd_lane_settings()
469 if (lt_settings->dpcd_lane_settings[lane].bits.VOLTAGE_SWING_SET in dp_is_max_vs_reached()
765 lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings); in override_training_settings()
852 union dpcd_training_lane *dpcd_lane_settings) in dp_decide_lane_settings() argument
871 dp_hw_to_dpcd_lane_settings(lt_settings, hw_lane_settings, dpcd_lane_settings); in dp_decide_lane_settings()
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H A Dlink_dp_training_128b_132b.c45 (uint8_t *)(link_training_setting->dpcd_lane_settings), in dpcd_128b_132b_set_lane_settings()
46 sizeof(link_training_setting->dpcd_lane_settings)); in dpcd_128b_132b_set_lane_settings()
51 link_training_setting->dpcd_lane_settings[0].tx_ffe.PRESET_VALUE); in dpcd_128b_132b_set_lane_settings()
96 lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings); in dp_perform_128b_132b_channel_eq_done_sequence()
114 lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings); in dp_perform_128b_132b_channel_eq_done_sequence()
252 lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings); in decide_128b_132b_training_settings()
H A Dlink_dp_training_8b_10b.c122 …to_dpcd_lane_settings(lt_settings, lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings); in decide_8b_10b_training_settings()
247 lt_settings->dpcd_lane_settings[0].bits.VOLTAGE_SWING_SET == in perform_8b_10b_clock_recovery_sequence()
251 lt_settings->dpcd_lane_settings[0].tx_ffe.PRESET_VALUE == in perform_8b_10b_clock_recovery_sequence()
259 lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings); in perform_8b_10b_clock_recovery_sequence()
350 lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings); in perform_8b_10b_channel_equalization_sequence()
403 lt_settings->dpcd_lane_settings[lane].raw = 0; in dp_perform_8b_10b_link_training()
H A Dlink_dp_training_dpia.c415 if ((lt_settings->dpcd_lane_settings[0].bits.VOLTAGE_SWING_SET == in dpia_training_cr_non_transparent()
417 && (lt_settings->dpcd_lane_settings[0].bits.PRE_EMPHASIS_SET == in dpia_training_cr_non_transparent()
426 lt_settings->dpcd_lane_settings); in dpia_training_cr_non_transparent()
519 if ((lt_settings->dpcd_lane_settings[0].bits.VOLTAGE_SWING_SET == in dpia_training_cr_transparent()
521 && (lt_settings->dpcd_lane_settings[0].bits.PRE_EMPHASIS_SET == in dpia_training_cr_transparent()
529 lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings); in dpia_training_cr_transparent()
698 lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings); in dpia_training_eq_non_transparent()
785 lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings); in dpia_training_eq_transparent()
H A Dlink_dp_training.h114 union dpcd_training_lane *dpcd_lane_settings);
160 union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX]);
H A Dlink_dp_phy.c131 lt_settings->dpcd_lane_settings); in dp_set_drive_settings()
/linux/drivers/gpu/drm/amd/display/include/
H A Dlink_service_types.h113 union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX]; member
/linux/drivers/gpu/drm/amd/display/dc/link/accessories/
H A Dlink_dp_cts.c258 link_training_settings.dpcd_lane_settings); in dp_test_send_phy_test_pattern()
402 link_training_settings.dpcd_lane_settings); in dp_test_send_phy_test_pattern()
653 p_link_settings->dpcd_lane_settings, in dp_set_test_pattern()