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Searched refs:dml_core_ctx (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddml2_wrapper_fpu.c76 if (dml2->v20.dml_core_ctx.project != dml_project_dcn35 && in map_hw_resources()
77 dml2->v20.dml_core_ctx.project != dml_project_dcn36 && in map_hw_resources()
78 dml2->v20.dml_core_ctx.project != dml_project_dcn351) { in map_hw_resources()
104 s->mode_support_params.mode_lib = &dml2->v20.dml_core_ctx; in pack_and_call_dml_mode_support_ex()
107 s->mode_support_params.in_start_state_idx = dml2->v20.dml_core_ctx.states.num_states - 1; in pack_and_call_dml_mode_support_ex()
169 build_unoptimized_policy_settings(dml2->v20.dml_core_ctx.project, &dml2->v20.dml_core_ctx.policy); in calculate_lowest_supported_state_for_temp_read()
194 for (i = 0; i < dml2->v20.dml_core_ctx.states.num_states; i++) { in calculate_lowest_supported_state_for_temp_read()
195 …s->uclk_change_latencies[i] = dml2->v20.dml_core_ctx.states.state_array[i].dram_clock_change_laten… in calculate_lowest_supported_state_for_temp_read()
199 for (j = 0; j < dml2->v20.dml_core_ctx.states.num_states; j++) { in calculate_lowest_supported_state_for_temp_read()
200 …dml2->v20.dml_core_ctx.states.state_array[j].dram_clock_change_latency_us = s_global->dummy_pstate… in calculate_lowest_supported_state_for_temp_read()
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H A Ddml2_wrapper.c63 (*dml2)->v20.dml_core_ctx.project = dml_project_dcn35; in dml2_init()
66 (*dml2)->v20.dml_core_ctx.project = dml_project_dcn351; in dml2_init()
69 (*dml2)->v20.dml_core_ctx.project = dml_project_dcn36; in dml2_init()
72 (*dml2)->v20.dml_core_ctx.project = dml_project_dcn32; in dml2_init()
75 (*dml2)->v20.dml_core_ctx.project = dml_project_dcn321; in dml2_init()
78 (*dml2)->v20.dml_core_ctx.project = dml_project_dcn401; in dml2_init()
81 (*dml2)->v20.dml_core_ctx.project = dml_project_default; in dml2_init()
85 initialize_dml2_ip_params(*dml2, in_dc, &(*dml2)->v20.dml_core_ctx.ip); in dml2_init()
87 initialize_dml2_soc_bbox(*dml2, in_dc, &(*dml2)->v20.dml_core_ctx.soc); in dml2_init()
89 …nitialize_dml2_soc_states(*dml2, in_dc, &(*dml2)->v20.dml_core_ctx.soc, &(*dml2)->v20.dml_core_ctx… in dml2_init()
H A Ddml2_utils.c286 …context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = (unsigned int)in_ctx->v20.dml_core_ctx.mp.DCFCL… in dml2_calculate_rq_and_dlg_params()
289 if (in_ctx->v20.dml_core_ctx.ms.support.FCLKChangeSupport[0] == dml_fclock_change_unsupported) in dml2_calculate_rq_and_dlg_params()
297 …context->bw_ctx.bw.dcn.compbuf_size_kb = in_ctx->v20.dml_core_ctx.ip.config_return_buffer_size_in_… in dml2_calculate_rq_and_dlg_params()
322 …ntext->res_ctx.pipe_ctx[dc_pipe_ctx_index], &context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx); in dml2_calculate_rq_and_dlg_params()
330 …er_size_kb = dml_get_det_buffer_size_kbytes(&context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx); in dml2_calculate_rq_and_dlg_params()
332 …context->res_ctx.pipe_ctx[dc_pipe_ctx_index].unbounded_req = in_ctx->v20.dml_core_ctx.ms.Unbounded… in dml2_calculate_rq_and_dlg_params()
336 ….bw.dppclk_khz = dml_get_dppclk_calculated(&context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx) … in dml2_calculate_rq_and_dlg_params()
340 dml_rq_dlg_get_rq_reg(&s->rq_regs, &in_ctx->v20.dml_core_ctx, dml_pipe_idx); in dml2_calculate_rq_and_dlg_params()
341 …dml_rq_dlg_get_dlg_reg(&s->disp_dlg_regs, &s->disp_ttu_regs, &in_ctx->v20.dml_core_ctx, dml_pipe_i… in dml2_calculate_rq_and_dlg_params()
344 …_mall_bytes = dml_get_surface_size_for_mall(&context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx); in dml2_calculate_rq_and_dlg_params()
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H A Ddml2_translation_helper.c37 switch (dml2->v20.dml_core_ctx.project) { in dml2_init_ip_params()
281 switch (dml2->v20.dml_core_ctx.project) { in dml2_init_socbb_params()
338 unsigned int dml_project = dml2->v20.dml_core_ctx.project; in dml2_init_soc_states()
357 switch (dml2->v20.dml_core_ctx.project) { in dml2_init_soc_states()
509 if ((dml2->v20.dml_core_ctx.project == dml_project_dcn32) || in dml2_init_soc_states()
510 (dml2->v20.dml_core_ctx.project == dml_project_dcn321)) { in dml2_init_soc_states()
516 } else if (dml2->v20.dml_core_ctx.project != dml_project_dcn35 && in dml2_init_soc_states()
517 dml2->v20.dml_core_ctx.project != dml_project_dcn36 && in dml2_init_soc_states()
518 dml2->v20.dml_core_ctx.project != dml_project_dcn351) { in dml2_init_soc_states()
565 if (dml2->v20.dml_core_ctx.project == dml_project_dcn35 || in dml2_init_soc_states()
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