Home
last modified time | relevance | path

Searched refs:dml_ceil (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddisplay_mode_vba_util_32.c222 dml_ceil((double) HTaps / 6.0, 1.0)); in dml32_CalculateSinglePipeDPPCLKAndSCLThroughput()
240 HRatioChroma / dml_ceil((double) HTapsChroma / 6.0, 1.0)); in dml32_CalculateSinglePipeDPPCLKAndSCLThroughput()
533 RoundedUpMaxSwathSizeBytesY[k] = dml_ceil((unsigned int) RoundedUpMaxSwathSizeBytesY[k], 256); in dml32_CalculateSwathAndDETConfiguration()
534 RoundedUpMaxSwathSizeBytesC[k] = dml_ceil((unsigned int) RoundedUpMaxSwathSizeBytesC[k], 256); in dml32_CalculateSwathAndDETConfiguration()
787 surface_width_ub_l = dml_ceil(SurfaceWidthY[k], Read256BytesBlockWidthY[k]); in dml32_CalculateSwathWidth()
788 surface_height_ub_l = dml_ceil(SurfaceHeightY[k], Read256BytesBlockHeightY[k]); in dml32_CalculateSwathWidth()
803 dml_ceil(SwathWidthY[k] - 1, in dml32_CalculateSwathWidth()
808 surface_width_ub_c = dml_ceil(SurfaceWidthC[k], Read256BytesBlockWidthC[k]); in dml32_CalculateSwathWidth()
818 dml_ceil(SwathWidthC[k] - 1, in dml32_CalculateSwathWidth()
835 swath_width_luma_ub[k] = dml_min(surface_height_ub_l, dml_ceil(SwathWidthY[k] - 1, in dml32_CalculateSwathWidth()
[all …]
H A Ddisplay_mode_vba_32.c700 dml_ceil((double) v->WritebackDelay[mode_lib->vba.VoltageLevel][k] in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1446 dml_ceil(v->WritebackDelay[mode_lib->vba.VoltageLevel][k] in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1833 v->ReadBandwidthLuma[k] = v->SwathWidthYSingleDPP[k] * dml_ceil(v->BytePerPixelInDETY[k], 1.0) in dml32_ModeSupportAndSystemConfigurationFull()
1835 …v->ReadBandwidthChroma[k] = v->SwathWidthYSingleDPP[k] / 2 * dml_ceil(v->BytePerPixelInDETC[k], 2.… in dml32_ModeSupportAndSystemConfigurationFull()
1940 / (mode_lib->vba.vtaps[k] + dml_max(dml_ceil(mode_lib->vba.VRatio[k], 1.0) - 2, 0.0)); in dml32_ModeSupportAndSystemConfigurationFull()
1947 + dml_max(dml_ceil(mode_lib->vba.VRatioChroma[k], 1.0) - 2, in dml32_ModeSupportAndSystemConfigurationFull()
2967 - dml_max(1.0, dml_ceil(1.0 * in dml32_ModeSupportAndSystemConfigurationFull()
3631 mode_lib->vba.AlignedYPitch[k] = dml_ceil( in dml32_ModeSupportAndSystemConfigurationFull()
3635 mode_lib->vba.AlignedDCCMetaPitchY[k] = dml_ceil( in dml32_ModeSupportAndSystemConfigurationFull()
3646 mode_lib->vba.AlignedCPitch[k] = dml_ceil( in dml32_ModeSupportAndSystemConfigurationFull()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddisplay_mode_vba_30.c896 Tvm_trips_rounded = dml_ceil(4.0 * Tvm_trips / LineTime, 1) / 4 * LineTime; in CalculatePrefetchSchedule()
897 Tr0_trips_rounded = dml_ceil(4.0 * Tr0_trips / LineTime, 1) / 4 * LineTime; in CalculatePrefetchSchedule()
932 Tvm_oto_lines = dml_ceil(4.0 * Tvm_oto / LineTime, 1) / 4.0; in CalculatePrefetchSchedule()
933 Tr0_oto_lines = dml_ceil(4.0 * Tr0_oto / LineTime, 1) / 4.0; in CalculatePrefetchSchedule()
1095 …*DestinationLinesToRequestVMInVBlank = dml_ceil(4.0 * TimeForFetchingMetaPTE / LineTime, 1.0) / 4.… in CalculatePrefetchSchedule()
1097 …*DestinationLinesToRequestRowInVBlank = dml_ceil(4.0 * TimeForFetchingRowInVBlank / LineTime, 1.0)… in CalculatePrefetchSchedule()
1209 return VCOSpeed * 4 / dml_ceil(VCOSpeed * 4.0 / Clock, 1); in RoundToDFSGranularityDown()
1351 full_swath_bytes_horz_wc_l = dml_ceil(full_swath_bytes_horz_wc_l * 2 / 3, 256); in CalculateDCCConfiguration()
1352 full_swath_bytes_horz_wc_c = dml_ceil(full_swath_bytes_horz_wc_c * 2 / 3, 256); in CalculateDCCConfiguration()
1353 full_swath_bytes_vert_wc_l = dml_ceil(full_swath_bytes_vert_wc_l * 2 / 3, 256); in CalculateDCCConfiguration()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_mode_vba.c1131 dml_ceil(WritebackLumaHTaps / 4.0, 1) / WritebackHRatio, in CalculateWriteBackDISPCLK()
1132 …dml_max((WritebackLumaVTaps * dml_ceil(1.0 / WritebackVRatio, 1) * dml_ceil(WritebackDestinationWi… in CalculateWriteBackDISPCLK()
1133 …+ dml_ceil(WritebackDestinationWidth / 4.0, 1)) / (double) HTotal + dml_ceil(1.0 / WritebackVRatio… in CalculateWriteBackDISPCLK()
1134 * (dml_ceil(WritebackLumaVTaps / 4.0, 1) + 4.0) / (double) HTotal, in CalculateWriteBackDISPCLK()
1135 dml_ceil(1.0 / WritebackVRatio, 1) * WritebackDestinationWidth / (double) HTotal)); in CalculateWriteBackDISPCLK()
1138 dml_ceil(WritebackChromaHTaps / 2.0, 1) / (2 * WritebackHRatio), in CalculateWriteBackDISPCLK()
1139 …dml_max((WritebackChromaVTaps * dml_ceil(1 / (2 * WritebackVRatio), 1) * dml_ceil(WritebackDestina… in CalculateWriteBackDISPCLK()
1140 + dml_ceil(WritebackDestinationWidth / 2.0 / WritebackChromaLineBufferWidth, 1)) / HTotal in CalculateWriteBackDISPCLK()
1141 … + dml_ceil(1 / (2 * WritebackVRatio), 1) * (dml_ceil(WritebackChromaVTaps / 4.0, 1) + 4) / HTotal, in CalculateWriteBackDISPCLK()
1142 dml_ceil(1.0 / (2 * WritebackVRatio), 1) * WritebackDestinationWidth / 2.0 / HTotal))); in CalculateWriteBackDISPCLK()
H A Ddml_inline_defs.h67 static inline double dml_ceil(double a, double granularity) in dml_ceil() function
H A Ddml1_display_rq_dlg_calc.c185 …*max_num_sw = (unsigned int) (dml_ceil((prefill - 1.0) / (double) swath_height, 1) + 1.0); /* pref… in get_swath_need()
447 + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); in dml1_rq_dlg_get_row_heights()
686 + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); in get_surf_rq_param()
922 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil( in get_surf_rq_param()
1845 cur0_width_ub = dml_ceil((double) cur0_src_width / (double) cur0_req_width, 1) in dml1_rq_dlg_get_dlg_params()
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddisplay_mode_core.c1157 s->Tvm_trips_rounded = dml_ceil(4.0 * s->Tvm_trips / s->LineTime, 1.0) / 4.0 * s->LineTime; in CalculatePrefetchSchedule()
1158 s->Tr0_trips_rounded = dml_ceil(4.0 * s->Tr0_trips / s->LineTime, 1.0) / 4.0 * s->LineTime; in CalculatePrefetchSchedule()
1162 …s->Tr0_trips_rounded = dml_ceil(4.0 * p->UrgentExtraLatency / s->LineTime, 1.0) / 4.0 * s->LineTim… in CalculatePrefetchSchedule()
1169 s->Tr0_trips_rounded = dml_ceil(4.0 * s->Tr0_trips / s->LineTime, 1.0) / 4.0 * s->LineTime; in CalculatePrefetchSchedule()
1196 …s->Lsw_oto = dml_ceil(4.0 * dml_max(s->prefetch_sw_bytes / s->prefetch_bw_oto / s->LineTime, s->mi… in CalculatePrefetchSchedule()
1221 s->Tvm_oto_lines = dml_ceil(4.0 * s->Tvm_oto / s->LineTime, 1) / 4.0; in CalculatePrefetchSchedule()
1222 s->Tr0_oto_lines = dml_ceil(4.0 * s->Tr0_oto / s->LineTime, 1) / 4.0; in CalculatePrefetchSchedule()
1416 …*p->DestinationLinesToRequestVMInVBlank = dml_ceil(4.0 * s->TimeForFetchingMetaPTE / s->LineTime, … in CalculatePrefetchSchedule()
1417 …*p->DestinationLinesToRequestRowInVBlank = dml_ceil(4.0 * s->TimeForFetchingRowInVBlank / s->LineT… in CalculatePrefetchSchedule()
1427 …*p->DestinationLinesToRequestVMInVBlank = dml_ceil(4.0 * s->TimeForFetchingMetaPTE / s->LineTime, … in CalculatePrefetchSchedule()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn351/
H A Ddcn351_fpu.c454 num_lines = dml_ceil(1000.0 * num_us / lines_time_in_ns, 1.0); in micro_sec_to_vert_lines()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn35/
H A Ddcn35_fpu.c421 num_lines = dml_ceil(1000.0 * num_us / lines_time_in_ns, 1.0); in micro_sec_to_vert_lines()