Searched refs:dml2_core_internal_soc_state_max (Results 1 – 2 of 2) sorted by relevance
178 dml2_core_internal_soc_state_max enumerator329 double avg_bandwidth_available_min[dml2_core_internal_soc_state_max];330 double avg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];331 …double urg_bandwidth_available_min_latency[dml2_core_internal_soc_state_max]; // min between SDP a…332 double urg_bandwidth_available_min[dml2_core_internal_soc_state_max]; // min between SDP and DRAM333 double urg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];334 …double urg_bandwidth_available_vm_only[dml2_core_internal_soc_state_max]; // the min of sdp bw and…335 …double urg_bandwidth_available_pixel_and_vm[dml2_core_internal_soc_state_max]; // the min of sdp b…337 double avg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];338 …double urg_vactive_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]…[all …]
330 case dml2_core_internal_soc_state_max: in dml2_core_utils_internal_soc_state_type_str()