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Searched refs:dm_write_reg (Results 1 – 18 of 18) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_opp_regamma_v.c68 dm_write_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL, value); in power_on_lut()
97 dm_write_reg(xfm_dce->base.ctx, in set_bypass_input_gamma()
111 dm_write_reg(xfm_dce->base.ctx, mmGAMMA_CORR_CONTROL, 0); in configure_regamma_mode()
149 dm_write_reg(xfm_dce->base.ctx, mmGAMMA_CORR_CNTLA_START_CNTL, in regamma_config_regions_and_segments()
160 dm_write_reg(xfm_dce->base.ctx, in regamma_config_regions_and_segments()
171 dm_write_reg(xfm_dce->base.ctx, in regamma_config_regions_and_segments()
188 dm_write_reg(xfm_dce->base.ctx, in regamma_config_regions_and_segments()
220 dm_write_reg( in regamma_config_regions_and_segments()
253 dm_write_reg(xfm_dce->base.ctx, in regamma_config_regions_and_segments()
285 dm_write_reg(xfm_dce->base.ctx, in regamma_config_regions_and_segments()
[all …]
H A Ddce110_mem_input_v.c53 dm_write_reg( in set_flip_control()
74 dm_write_reg( in program_pri_addr_c()
87 dm_write_reg( in program_pri_addr_c()
109 dm_write_reg( in program_pri_addr_l()
122 dm_write_reg( in program_pri_addr_l()
158 dm_write_reg(mem_input110->base.ctx, in enable()
200 dm_write_reg( in program_tiling()
222 dm_write_reg( in program_tiling()
253 dm_write_reg( in program_size_and_rotation()
261 dm_write_reg( in program_size_and_rotation()
[all …]
H A Ddce110_opp_csc_v.c142 dm_write_reg(ctx, addr, value); in program_color_matrix_v()
160 dm_write_reg(ctx, addr, value); in program_color_matrix_v()
178 dm_write_reg(ctx, addr, value); in program_color_matrix_v()
196 dm_write_reg(ctx, addr, value); in program_color_matrix_v()
214 dm_write_reg(ctx, addr, value); in program_color_matrix_v()
232 dm_write_reg(ctx, addr, value); in program_color_matrix_v()
256 dm_write_reg(ctx, addr, value); in program_color_matrix_v()
274 dm_write_reg(ctx, addr, value); in program_color_matrix_v()
292 dm_write_reg(ctx, addr, value); in program_color_matrix_v()
310 dm_write_reg(ctx, addr, value); in program_color_matrix_v()
[all …]
H A Ddce110_timing_generator_v.c64 dm_write_reg(tg->ctx, in dce110_timing_generator_v_enable_crtc()
69 dm_write_reg(tg->ctx, mmCRTCV_MASTER_UPDATE_MODE, value); in dce110_timing_generator_v_enable_crtc()
74 dm_write_reg(tg->ctx, in dce110_timing_generator_v_enable_crtc()
90 dm_write_reg(tg->ctx, in dce110_timing_generator_v_disable_crtc()
116 dm_write_reg(tg->ctx, addr, value); in dce110_timing_generator_v_blank_crtc()
136 dm_write_reg(tg->ctx, addr, value); in dce110_timing_generator_v_unblank_crtc()
265 dm_write_reg(ctx, addr, value); in dce110_timing_generator_v_program_blanking()
274 dm_write_reg(ctx, addr, value); in dce110_timing_generator_v_program_blanking()
297 dm_write_reg(ctx, addr, value); in dce110_timing_generator_v_program_blanking()
319 dm_write_reg(ctx, addr, value); in dce110_timing_generator_v_program_blanking()
[all …]
H A Ddce110_timing_generator.c116 dm_write_reg(tg->ctx, address, regval); in dce110_timing_generator_set_early_control()
140 dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_MODE), value); in dce110_timing_generator_enable_crtc()
144 dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_LOCK), value); in dce110_timing_generator_enable_crtc()
175 dm_write_reg(tg->ctx, addr, value); in dce110_timing_generator_program_blank_color()
222 dm_write_reg(tg->ctx, addr, value);
225 dm_write_reg(tg->ctx, addr, value);
271 dm_write_reg(tg->ctx, in program_horz_count_by_2()
460 dm_write_reg(tg->ctx, addr, v_total_min); in dce110_timing_generator_set_drr()
463 dm_write_reg(tg->ctx, addr, v_total_max); in dce110_timing_generator_set_drr()
466 dm_write_reg(tg->ctx, addr, v_total_cntl); in dce110_timing_generator_set_drr()
[all …]
H A Ddce110_transform_v.c99 dm_write_reg(ctx, addr, value); in program_viewport()
113 dm_write_reg(ctx, addr, value); in program_viewport()
129 dm_write_reg(ctx, addr, value); in program_viewport()
143 dm_write_reg(ctx, addr, value); in program_viewport()
173 dm_write_reg(ctx, mmSCLV_TAP_CONTROL, value); in setup_scaling_configuration()
204 dm_write_reg(ctx, mmSCLV_MODE, value); in setup_scaling_configuration()
213 dm_write_reg(ctx, mmSCLV_CONTROL, value); in setup_scaling_configuration()
263 dm_write_reg(xfm_dce->base.ctx, in program_overscan()
267 dm_write_reg(xfm_dce->base.ctx, in program_overscan()
279 dm_write_reg(xfm_dce->base.ctx, mmSCLV_UPDATE, value); in set_coeff_update_complete()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce112/
H A Ddce112_compressor.c334 dm_write_reg(compressor->ctx, addr, value); in dce112_compressor_power_up_fbc()
341 dm_write_reg(compressor->ctx, addr, value); in dce112_compressor_power_up_fbc()
346 dm_write_reg(compressor->ctx, addr, value); in dce112_compressor_power_up_fbc()
352 dm_write_reg(compressor->ctx, addr, value); in dce112_compressor_power_up_fbc()
356 dm_write_reg(compressor->ctx, mmFBC_IND_LUT0, value); in dce112_compressor_power_up_fbc()
359 dm_write_reg(compressor->ctx, mmFBC_IND_LUT1, value); in dce112_compressor_power_up_fbc()
397 dm_write_reg(compressor->ctx, addr, value); in dce112_compressor_enable_fbc()
406 dm_write_reg(compressor->ctx, addr, value); in dce112_compressor_enable_fbc()
408 dm_write_reg(compressor->ctx, addr, value); in dce112_compressor_enable_fbc()
424 dm_write_reg(compressor->ctx, mmFBC_CNTL, reg_data); in dce112_compressor_disable_fbc()
[all …]
/linux/drivers/net/usb/
H A Ddm9601.c89 static int dm_write_reg(struct usbnet *dev, u8 reg, u8 value) in dm_write_reg() function
117 dm_write_reg(dev, DM_SHARED_ADDR, phy ? (reg | 0x40) : reg); in dm_read_shared_word()
118 dm_write_reg(dev, DM_SHARED_CTRL, phy ? 0xc : 0x4); in dm_read_shared_word()
139 dm_write_reg(dev, DM_SHARED_CTRL, 0x0); in dm_read_shared_word()
160 dm_write_reg(dev, DM_SHARED_ADDR, phy ? (reg | 0x40) : reg); in dm_write_shared_word()
161 dm_write_reg(dev, DM_SHARED_CTRL, phy ? 0x1a : 0x12); in dm_write_shared_word()
182 dm_write_reg(dev, DM_SHARED_CTRL, 0x0); in dm_write_shared_word()
386 dm_write_reg(dev, DM_NET_CTRL, 1); in dm9601_bind()
423 dm_write_reg(dev, DM_MODE_CTRL, mode & 0x7f); in dm9601_bind()
427 dm_write_reg(dev, DM_GPR_CTRL, 1); in dm9601_bind()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce60/
H A Ddce60_timing_generator.c105 dm_write_reg(tg->ctx, addr, value); in program_pix_dur()
175 dm_write_reg(tg->ctx, addr, value); in dce60_timing_generator_enable_advanced_request()
176 dm_write_reg(tg->ctx, addr2, value2); in dce60_timing_generator_enable_advanced_request()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dce112/
H A Ddce112_hwseq.c109 dm_write_reg(ctx, addr, value); in dce112_init_pte()
138 dm_write_reg(ctx, in dce112_enable_display_power_gating()
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn321/
H A Ddcn321_dio_link_encoder.c60 dm_write_reg(CTX, AUX_REG(reg_name), val)
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn30/
H A Ddcn30_dio_link_encoder.c215 dm_write_reg(CTX, AUX_REG(reg_name), val)
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn401/
H A Ddcn401_dio_link_encoder.c62 dm_write_reg(CTX, AUX_REG(reg_name), val)
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn32/
H A Ddcn32_dio_link_encoder.c63 dm_write_reg(CTX, AUX_REG(reg_name), val)
/linux/drivers/gpu/drm/amd/display/dc/irq/dce110/
H A Dirq_service_dce110.c59 dm_write_reg(irq_service->ctx, info->enable_reg, value); in hpd_ack()
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn20/
H A Ddcn20_link_encoder.c307 dm_write_reg(CTX, AUX_REG(reg_name), val)
/linux/drivers/gpu/drm/amd/display/dc/bios/
H A Dbios_parser.c816 dm_write_reg(ctx, bp->base.regs->BIOS_SCRATCH_0, bios_0_scratch); in bios_parser_dac_load_detection()
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm.c2434 return dm_write_reg(adev->dm.dc->ctx, address, value); in amdgpu_dm_dmub_reg_write()