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Searched refs:dm_read_reg (Results 1 – 17 of 17) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_compressor.c80 status_pos = dm_read_reg(compressor->ctx, DCP_REG(mmCRTC_STATUS_POSITION)); in reset_lb_on_vblank()
84 if (status_pos != dm_read_reg(compressor->ctx, DCP_REG(mmCRTC_STATUS_POSITION))) { in reset_lb_on_vblank()
86 value = dm_read_reg(compressor->ctx, DCP_REG(mmLB_SYNC_RESET_SEL)); in reset_lb_on_vblank()
91 frame_count = dm_read_reg(compressor->ctx, DCP_REG(mmCRTC_STATUS_FRAME_COUNT)); in reset_lb_on_vblank()
95 if (frame_count != dm_read_reg(compressor->ctx, DCP_REG(mmCRTC_STATUS_FRAME_COUNT))) in reset_lb_on_vblank()
103 value = dm_read_reg(compressor->ctx, DCP_REG(mmLB_SYNC_RESET_SEL)); in reset_lb_on_vblank()
119 value = dm_read_reg(cp110->base.ctx, addr); in wait_for_fbc_state_changed()
145 value = dm_read_reg(compressor->ctx, addr); in dce110_compressor_power_up_fbc()
160 value = dm_read_reg(compressor->ctx, addr); in dce110_compressor_power_up_fbc()
167 value = dm_read_reg(compressor->ctx, addr); in dce110_compressor_power_up_fbc()
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H A Ddce110_mem_input_v.c45 value = dm_read_reg( in set_flip_control()
156 value = dm_read_reg(mem_input110->base.ctx, mmUNP_GRPH_ENABLE); in enable()
369 value = dm_read_reg( in program_pixel_format()
422 value = dm_read_reg( in program_pixel_format()
442 value = dm_read_reg( in program_pixel_format()
476 value = dm_read_reg(mem_input110->base.ctx, mmUNP_GRPH_UPDATE); in dce_mem_input_v_is_surface_pending()
607 value = dm_read_reg(mem_input110->base.ctx, mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT); in dce_mem_input_v_program_pte_vm()
613 value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_CONTROL); in dce_mem_input_v_program_pte_vm()
619 value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_ARB_CONTROL); in dce_mem_input_v_program_pte_vm()
624 value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_CONTROL_C); in dce_mem_input_v_program_pte_vm()
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H A Ddce110_timing_generator_v.c84 value = dm_read_reg(tg->ctx, in dce110_timing_generator_v_disable_crtc()
102 uint32_t value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_v_blank_crtc()
122 uint32_t value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_v_unblank_crtc()
147 value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_v_is_in_vertical_blank()
160 value = dm_read_reg(tg->ctx, mmCRTCV_STATUS_POSITION); in dce110_timing_generator_v_is_counter_moving()
172 value = dm_read_reg(tg->ctx, mmCRTCV_STATUS_POSITION); in dce110_timing_generator_v_is_counter_moving()
259 value = dm_read_reg(ctx, addr); in dce110_timing_generator_v_program_blanking()
268 value = dm_read_reg(ctx, addr); in dce110_timing_generator_v_program_blanking()
277 value = dm_read_reg(ctx, addr); in dce110_timing_generator_v_program_blanking()
300 value = dm_read_reg(ctx, addr); in dce110_timing_generator_v_program_blanking()
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H A Ddce110_timing_generator.c100 value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_is_in_vertical_blank()
113 regval = dm_read_reg(tg->ctx, address); in dce110_timing_generator_set_early_control()
157 uint32_t value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_program_blank_color()
199 value = dm_read_reg(tg->ctx, addr);
261 regval = dm_read_reg(tg->ctx, in program_horz_count_by_2()
378 v_total_min = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_set_drr()
381 v_total_max = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_set_drr()
384 v_total_cntl = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_set_drr()
483 static_screen_cntl = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_set_static_screen_control()
516 uint32_t value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_get_vblank_counter()
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H A Ddce110_opp_regamma_v.c37 uint32_t value = dm_read_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL); in power_on_lut()
71 value = dm_read_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL); in power_on_lut()
88 value = dm_read_reg(xfm_dce->base.ctx, in set_bypass_input_gamma()
521 uint32_t value = dm_read_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL); in dce110_opp_power_on_regamma_lut_v()
H A Ddce110_opp_csc_v.c114 uint32_t cntl_value = dm_read_reg(ctx, mmCOL_MAN_OUTPUT_CSC_CONTROL); in program_color_matrix_v()
366 uint32_t value = dm_read_reg(ctx, addr); in configure_graphics_mode_v()
465 uint32_t value = dm_read_reg(xfm->ctx, mmDENORM_CLAMP_CONTROL); in set_Denormalization()
555 value = dm_read_reg(ctx, mmCOL_MAN_INPUT_CSC_CONTROL); in program_input_csc()
H A Ddce110_transform_v.c277 value = dm_read_reg(xfm_dce->base.ctx, mmSCLV_UPDATE); in set_coeff_update_complete()
301 power_ctl = dm_read_reg(ctx, mmDCFEV_MEM_PWR_CTRL); in program_multi_taps_filter()
309 dm_read_reg(ctx, mmDCFEV_MEM_PWR_STATUS), in program_multi_taps_filter()
508 value = dm_read_reg(xfm_dce->base.ctx, mmLBV_MEMORY_CTRL); in dce110_xfmv_power_up_line_buffer()
/linux/drivers/gpu/drm/amd/display/dc/dce112/
H A Ddce112_compressor.c299 value = dm_read_reg(cp110->base.ctx, addr); in wait_for_fbc_state_changed()
322 value = dm_read_reg(compressor->ctx, addr); in dce112_compressor_power_up_fbc()
337 value = dm_read_reg(compressor->ctx, addr); in dce112_compressor_power_up_fbc()
344 value = dm_read_reg(compressor->ctx, addr); in dce112_compressor_power_up_fbc()
391 value = dm_read_reg(compressor->ctx, addr); in dce112_compressor_enable_fbc()
422 reg_data = dm_read_reg(compressor->ctx, mmFBC_CNTL); in dce112_compressor_disable_fbc()
446 value = dm_read_reg(compressor->ctx, mmFBC_STATUS); in dce112_compressor_is_fbc_enabled_in_hw()
453 value = dm_read_reg(compressor->ctx, mmFBC_MISC); in dce112_compressor_is_fbc_enabled_in_hw()
455 value = dm_read_reg(compressor->ctx, mmFBC_CNTL); in dce112_compressor_is_fbc_enabled_in_hw()
470 uint32_t value = dm_read_reg(compressor->ctx, in dce112_compressor_is_lpt_enabled_in_hw()
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/linux/drivers/gpu/drm/amd/display/dc/dce60/
H A Ddce60_timing_generator.c92 uint32_t value = dm_read_reg(tg->ctx, addr); in program_pix_dur()
131 uint32_t value = dm_read_reg(tg->ctx, addr); in dce60_timing_generator_enable_advanced_request()
134 uint32_t value2 = dm_read_reg(tg->ctx, addr2); in dce60_timing_generator_enable_advanced_request()
187 value = dm_read_reg(tg->ctx, addr); in dce60_is_tg_enabled()
/linux/drivers/net/usb/
H A Ddm9601.c72 static int dm_read_reg(struct usbnet *dev, u8 reg, u8 *value) in dm_read_reg() function
124 ret = dm_read_reg(dev, DM_SHARED_CTRL, &tmp); in dm_read_shared_word()
167 ret = dm_read_reg(dev, DM_SHARED_CTRL, &tmp); in dm_write_shared_word()
387 if (dm_read_reg(dev, DM_CHIP_ID, &id) < 0) { in dm9601_bind()
397 if (dm_read_reg(dev, DM_MODE_CTRL, &mode) < 0) { in dm9601_bind()
/linux/drivers/gpu/drm/amd/display/dc/irq/dce110/
H A Dirq_service_dce110.c46 uint32_t value = dm_read_reg(irq_service->ctx, addr); in hpd_ack()
53 value = dm_read_reg(irq_service->ctx, info->enable_reg); in hpd_ack()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dce112/
H A Ddce112_hwseq.c77 value = dm_read_reg(ctx, addr); in dce112_init_pte()
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_link_encoder.c652 uint32_t value = dm_read_reg(ctx, addr); in aux_initialize()
659 value = dm_read_reg(ctx, addr); in aux_initialize()
1759 uint32_t value = dm_read_reg(ctx, addr); in dce110_link_encoder_enable_hpd()
1772 uint32_t value = dm_read_reg(ctx, addr); in dce110_link_encoder_disable_hpd()
H A Ddce_dmcu.c1097 psp_version = dm_read_reg(ctx, mmMP0_SMN_C2PMSG_58); in dcn21_dmcu_construct()
/linux/drivers/gpu/drm/amd/display/dc/bios/
H A Dbios_parser.c814 bios_0_scratch = dm_read_reg(ctx, bp->base.regs->BIOS_SCRATCH_0); in bios_parser_dac_load_detection()
823 bios_0_scratch = dm_read_reg(ctx, bp->base.regs->BIOS_SCRATCH_0); in bios_parser_dac_load_detection()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/
H A Ddce110_hwseq.c140 value = dm_read_reg(ctx, addr); in dce110_init_pte()
163 value = dm_read_reg(ctx, addr); in dce110_init_pte()
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm.c2422 return dm_read_reg(adev->dm.dc->ctx, address); in amdgpu_dm_dmub_reg_read()