| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn21/ |
| H A D | dcn21_hubp.c | 359 DLG_V_BLANK_END, &dlg_attr.dlg_vblank_end); in hubp21_validate_dml_output()
373 if (dlg_attr.dlg_vblank_end != dml_dlg_attr->dlg_vblank_end) in hubp21_validate_dml_output()
375 dml_dlg_attr->dlg_vblank_end, dlg_attr.dlg_vblank_end); in hubp21_validate_dml_output()
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| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn20/ |
| H A D | dcn20_hubp.c | 91 DLG_V_BLANK_END, dlg_attr->dlg_vblank_end); in hubp2_program_deadline()
1157 DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end); in hubp2_read_state_common()
1468 DLG_V_BLANK_END, &dlg_attr.dlg_vblank_end); in hubp2_validate_dml_output()
1482 if (dlg_attr.dlg_vblank_end != dml_dlg_attr->dlg_vblank_end) in hubp2_validate_dml_output()
1484 dml_dlg_attr->dlg_vblank_end, dlg_attr.dlg_vblank_end); in hubp2_validate_dml_output()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/ |
| H A D | dml_top_dchub_registers.h | 13 uint32_t dlg_vblank_end; member
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| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_rq_dlg_helpers.c | 200 dlg_regs->dlg_vblank_end); in print__dlg_regs_st()
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| H A D | display_mode_structs.h | 622 unsigned int dlg_vblank_end; member
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| H A D | dml1_display_rq_dlg_calc.c | 1159 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; /* 15 bits */ in dml1_rq_dlg_get_dlg_params()
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| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn401/ |
| H A D | dcn401_hubp.c | 224 DLG_V_BLANK_END, dlg_attr->dlg_vblank_end); in hubp401_program_deadline()
825 DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end); in hubp401_read_state()
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| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn10/ |
| H A D | dcn10_hubp.c | 616 DLG_V_BLANK_END, dlg_attr->dlg_vblank_end); in hubp1_program_deadline()
926 DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end); in hubp1_read_state_common()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | display_rq_dlg_calc_32.c | 277 dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits in dml32_rq_dlg_get_dlg_reg()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/ |
| H A D | dml_display_rq_dlg_calc.c | 320 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits in dml_rq_dlg_get_dlg_reg()
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| H A D | dml2_translation_helper.c | 1476 out->dlg_regs.dlg_vblank_end = disp_dlg_regs->dlg_vblank_end; in dml2_update_pipe_ctx_dchub_regs()
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| H A D | display_mode_util.c | 254 dml_print("DML: dlg_vblank_end = 0x%x\n", dlg_regs->dlg_vblank_end); in dml_print_dlg_regs_st()
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| H A D | display_mode_core_structs.h | 1931 dml_uint_t dlg_vblank_end; member
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | display_rq_dlg_calc_20.c | 924 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits in dml20_rq_dlg_get_dlg_params()
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| H A D | display_rq_dlg_calc_20v2.c | 924 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits in dml20v2_rq_dlg_get_dlg_params()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| H A D | display_rq_dlg_calc_21.c | 970 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits in dml_rq_dlg_get_dlg_params()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| H A D | display_rq_dlg_calc_30.c | 1041 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits in dml_rq_dlg_get_dlg_params()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/ |
| H A D | dml2_core_shared.c | 11696 disp_dlg_regs->dlg_vblank_end = l->interlaced ? (l->vblank_end / 2) : l->vblank_end; // 15 bits in rq_dlg_get_dlg_reg()
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| H A D | dml2_core_dcn4_calcs.c | 12457 disp_dlg_regs->dlg_vblank_end = l->interlaced ? (l->vblank_end / 2) : l->vblank_end; // 15 bits in rq_dlg_get_dlg_reg()
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