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Searched refs:dlg_regs (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddisplay_mode_util.c251 void dml_print_dlg_regs_st(const dml_display_dlg_regs_st *dlg_regs) in dml_print_dlg_regs_st() argument
253 (void)dlg_regs; in dml_print_dlg_regs_st()
256 dml_print("DML: refcyc_h_blank_end = 0x%x\n", dlg_regs->refcyc_h_blank_end); in dml_print_dlg_regs_st()
257 dml_print("DML: dlg_vblank_end = 0x%x\n", dlg_regs->dlg_vblank_end); in dml_print_dlg_regs_st()
258 dml_print("DML: min_dst_y_next_start = 0x%x\n", dlg_regs->min_dst_y_next_start); in dml_print_dlg_regs_st()
259 dml_print("DML: refcyc_per_htotal = 0x%x\n", dlg_regs->refcyc_per_htotal); in dml_print_dlg_regs_st()
260 dml_print("DML: refcyc_x_after_scaler = 0x%x\n", dlg_regs->refcyc_x_after_scaler); in dml_print_dlg_regs_st()
261 dml_print("DML: dst_y_after_scaler = 0x%x\n", dlg_regs->dst_y_after_scaler); in dml_print_dlg_regs_st()
262 dml_print("DML: dst_y_prefetch = 0x%x\n", dlg_regs->dst_y_prefetch); in dml_print_dlg_regs_st()
263 dml_print("DML: dst_y_per_vm_vblank = 0x%x\n", dlg_regs->dst_y_per_vm_vblank); in dml_print_dlg_regs_st()
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H A Ddml2_translation_helper.c1465 memset(&out->dlg_regs, 0, sizeof(out->dlg_regs)); in dml2_update_pipe_ctx_dchub_regs()
1466 out->dlg_regs.refcyc_h_blank_end = disp_dlg_regs->refcyc_h_blank_end; in dml2_update_pipe_ctx_dchub_regs()
1467 out->dlg_regs.dlg_vblank_end = disp_dlg_regs->dlg_vblank_end; in dml2_update_pipe_ctx_dchub_regs()
1468 out->dlg_regs.min_dst_y_next_start = disp_dlg_regs->min_dst_y_next_start; in dml2_update_pipe_ctx_dchub_regs()
1469 out->dlg_regs.refcyc_per_htotal = disp_dlg_regs->refcyc_per_htotal; in dml2_update_pipe_ctx_dchub_regs()
1470 out->dlg_regs.refcyc_x_after_scaler = disp_dlg_regs->refcyc_x_after_scaler; in dml2_update_pipe_ctx_dchub_regs()
1471 out->dlg_regs.dst_y_after_scaler = disp_dlg_regs->dst_y_after_scaler; in dml2_update_pipe_ctx_dchub_regs()
1472 out->dlg_regs.dst_y_prefetch = disp_dlg_regs->dst_y_prefetch; in dml2_update_pipe_ctx_dchub_regs()
1473 out->dlg_regs.dst_y_per_vm_vblank = disp_dlg_regs->dst_y_per_vm_vblank; in dml2_update_pipe_ctx_dchub_regs()
1474 out->dlg_regs.dst_y_per_row_vblank = disp_dlg_regs->dst_y_per_row_vblank; in dml2_update_pipe_ctx_dchub_regs()
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/linux/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_mode_lib.h53 display_dlg_regs_st *dlg_regs,
71 display_dlg_regs_st *dlg_regs,
H A Ddml1_display_rq_dlg_calc.h56 struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddisplay_rq_dlg_calc_32.h64 display_dlg_regs_st *dlg_regs,
H A Ddcn32_fpu.c1763 &context->res_ctx.pipe_ctx[i].dlg_regs, &context->res_ctx.pipe_ctx[i].ttu_regs, pipes, in dcn32_calculate_dlg_params()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/
H A Ddisplay_rq_dlg_calc_21.h62 display_dlg_regs_st *dlg_regs,
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddisplay_rq_dlg_calc_20.h62 display_dlg_regs_st *dlg_regs,
H A Ddisplay_rq_dlg_calc_20v2.h62 display_dlg_regs_st *dlg_regs,
H A Ddcn20_fpu.c1235 &context->res_ctx.pipe_ctx[i].dlg_regs, in dcn20_calculate_dlg_params()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddisplay_rq_dlg_calc_31.h58 display_dlg_regs_st *dlg_regs,
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/
H A Ddisplay_rq_dlg_calc_314.h59 display_dlg_regs_st *dlg_regs,
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddisplay_rq_dlg_calc_30.h58 display_dlg_regs_st *dlg_regs,
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_hw_sequencer.c2997 struct _vcs_dpi_display_dlg_regs_st *dlg_regs = params->hubp_setup_params.dlg_regs; in hwss_hubp_setup() local
3003 hubp->funcs->hubp_setup(hubp, dlg_regs, ttu_regs, rq_regs, pipe_dest); in hwss_hubp_setup()
3027 struct _vcs_dpi_display_dlg_regs_st *dlg_regs = params->hubp_setup_interdependent_params.dlg_regs; in hwss_hubp_setup_interdependent() local
3031 hubp->funcs->hubp_setup_interdependent(hubp, dlg_regs, ttu_regs); in hwss_hubp_setup_interdependent()
3860 struct _vcs_dpi_display_dlg_regs_st *dlg_regs, in hwss_add_hubp_setup() argument
3868 seq_state->steps[*seq_state->num_steps].params.hubp_setup_params.dlg_regs = dlg_regs; in hwss_add_hubp_setup()
3902 struct _vcs_dpi_display_dlg_regs_st *dlg_regs, in hwss_add_hubp_setup_interdependent() argument
3908 …eq_state->steps[*seq_state->num_steps].params.hubp_setup_interdependent_params.dlg_regs = dlg_regs; in hwss_add_hubp_setup_interdependent()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c1391 pipe_ctx->hubp_regs.dlg_regs.min_dst_y_next_start); in dcn401_optimize_bandwidth()
2820 struct dml2_display_dlg_regs old_dlg_regs = old_pipe->hubp_regs.dlg_regs; in dcn401_detect_pipe_changes()
2823 struct dml2_display_dlg_regs *new_dlg_regs = &new_pipe->hubp_regs.dlg_regs; in dcn401_detect_pipe_changes()
3547 hwss_add_hubp_setup(seq_state, hubp, &pipe_ctx->dlg_regs, in dcn401_update_dchubp_dpp_sequence()
3561 hwss_add_hubp_setup_interdependent(seq_state, hubp, &pipe_ctx->dlg_regs, &pipe_ctx->ttu_regs); in dcn401_update_dchubp_dpp_sequence()
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/
H A Ddml2_core_dcn4_calcs.c12796 …rq_dlg_get_dlg_reg(&mode_lib->scratch, &out->dlg_regs, &out->ttu_regs, display_cfg, mode_lib, pipe… in dml2_core_calcs_get_pipe_regs()