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Searched refs:divq (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/clk/
H A Dclk-highbank.c96 unsigned long divf, divq, vco_freq, reg; in clk_pll_recalc_rate() local
103 divq = (reg & HB_PLL_DIVQ_MASK) >> HB_PLL_DIVQ_SHIFT; in clk_pll_recalc_rate()
106 return vco_freq / (1 << divq); in clk_pll_recalc_rate()
112 u32 divq, divf; in clk_pll_calc() local
120 for (divq = 1; divq <= 6; divq++) { in clk_pll_calc()
121 if ((rate * (1 << divq)) >= HB_PLL_VCO_MIN_FREQ) in clk_pll_calc()
125 vco_freq = rate * (1 << divq); in clk_pll_calc()
129 *pdivq = divq; in clk_pll_calc()
136 u32 divq, divf; in clk_pll_round_rate() local
139 clk_pll_calc(rate, ref_freq, &divq, &divf); in clk_pll_round_rate()
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/linux/drivers/clk/imx/
H A Dclk-sscg-pll.c74 int divq; member
133 for (temp_setup->divq = 0; temp_setup->divq <= PLL_DIVQ_MAX; in clk_sscg_divq_lookup()
134 temp_setup->divq++) { in clk_sscg_divq_lookup()
142 do_div(temp_setup->fout, 2 * (temp_setup->divq + 1)); in clk_sscg_divq_lookup()
331 u32 val, divr1, divf1, divr2, divf2, divq; in clk_sscg_pll_recalc_rate() local
339 divq = FIELD_GET(PLL_DIVQ_MASK, val); in clk_sscg_pll_recalc_rate()
348 do_div(temp64, (divr2 + 1) * (divq + 1)); in clk_sscg_pll_recalc_rate()
352 do_div(temp64, (divr1 + 1) * (divr2 + 1) * (divq + 1)); in clk_sscg_pll_recalc_rate()
378 val |= FIELD_PREP(PLL_DIVQ_MASK, setup->divq); in clk_sscg_pll_set_rate()
H A Dclk-frac-pll.c100 u32 val, divff, divfi, divq; in clk_pll_recalc_rate() local
105 divq = (FIELD_GET(PLL_OUTPUT_DIV_MASK, val) + 1) * 2; in clk_pll_recalc_rate()
113 do_div(temp64, divq); in clk_pll_recalc_rate()
116 do_div(rate, divq); in clk_pll_recalc_rate()
/linux/drivers/clk/socfpga/
H A Dclk-pll.c42 unsigned long divf, divq, reg; in clk_pll_recalc_rate() local
52 divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT; in clk_pll_recalc_rate()
54 do_div(vco_freq, (1 + divq)); in clk_pll_recalc_rate()
/linux/include/linux/clk/
H A Danalogbits-wrpll-cln28hpc.h60 u8 divq; member
/linux/drivers/clk/sifive/
H A Dsifive-prci.c72 c->divq = v; in __prci_wrpll_unpack()
106 r |= c->divq << PRCI_COREPLLCFG0_DIVQ_SHIFT; in __prci_wrpll_pack()