Searched refs:divider_reg (Results 1 – 4 of 4) sorted by relevance
435 void __iomem *divider_reg; /* CSR for divider */ member543 if (pclk->param.divider_reg) { in xgene_clk_recalc_rate()544 data = xgene_clk_read(pclk->param.divider_reg + in xgene_clk_recalc_rate()573 if (pclk->param.divider_reg) { in xgene_clk_set_rate()582 data = xgene_clk_read(pclk->param.divider_reg + in xgene_clk_set_rate()587 xgene_clk_write(data, pclk->param.divider_reg + in xgene_clk_set_rate()608 if (pclk->param.divider_reg) { in xgene_clk_determine_rate()687 parameters.divider_reg = NULL; in xgene_devclk_init()704 parameters.divider_reg = map_res; in xgene_devclk_init()742 if (parameters.divider_reg) in xgene_devclk_init()[all …]
39 unsigned int divider_reg; member77 .divider_reg = AP806_CA72MP2_0_PLL_CR_0_REG_OFFSET,111 .divider_reg = AP807_DEVICE_GENERAL_CONTROL_10_REG_OFFSET,150 cpu_clkdiv_reg = clk->pll_regs->divider_reg + in ap_cpu_clk_recalc_rate()166 cpu_clkdiv_reg = clk->pll_regs->divider_reg + in ap_cpu_clk_set_rate()
99 uint32_t divider_reg; member169 .divider_reg = _div_reg, \189 .divider_reg = _div_reg, \
276 div->reg = base + mc->divider_reg; in mtk_clk_register_composite()