Searched refs:divided_rate (Results 1 – 2 of 2) sorted by relevance
381 u32 rate, divided_rate = 0; in tcb_clksrc_init() local447 divided_rate = tmp; in tcb_clksrc_init()453 pr_debug("%s at %d.%03d MHz\n", clksrc.name, divided_rate / 1000000, in tcb_clksrc_init()454 ((divided_rate % 1000000) + 500) / 1000); in tcb_clksrc_init()481 ret = clocksource_register_hz(&clksrc, divided_rate); in tcb_clksrc_init()490 sched_clock_register(tc_sched_clock, 32, divided_rate); in tcb_clksrc_init()492 tc_delay_timer.freq = divided_rate; in tcb_clksrc_init()
172 unsigned long divided_rate; in emc_determine_rate() local195 divided_rate = DIV_ROUND_UP(parent_rate * 2, div + 2); in emc_determine_rate()197 if (divided_rate != emc_rate) in emc_determine_rate()