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Searched refs:divf (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/clk/
H A Dclk-highbank.c96 unsigned long divf, divq, vco_freq, reg; in clk_pll_recalc_rate() local
102 divf = (reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT; in clk_pll_recalc_rate()
104 vco_freq = parent_rate * (divf + 1); in clk_pll_recalc_rate()
112 u32 divq, divf; in clk_pll_calc() local
126 divf = (vco_freq + (ref_freq / 2)) / ref_freq; in clk_pll_calc()
127 divf--; in clk_pll_calc()
130 *pdivf = divf; in clk_pll_calc()
136 u32 divq, divf; in clk_pll_determine_rate() local
139 clk_pll_calc(req->rate, ref_freq, &divq, &divf); in clk_pll_determine_rate()
141 req->rate = (ref_freq * (divf + 1)) / (1 << divq); in clk_pll_determine_rate()
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/linux/drivers/clk/socfpga/
H A Dclk-pll.c42 u32 divf, divq, reg; in clk_pll_recalc_rate() local
51 divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT; in clk_pll_recalc_rate()
53 vco_freq = (unsigned long long)parent_rate * (divf + 1); in clk_pll_recalc_rate()
H A Dclk-pll-a10.c38 u32 divf, divq, reg; in clk_pll_recalc_rate() local
43 divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT; in clk_pll_recalc_rate()
45 vco_freq = (unsigned long long)parent_rate * (divf + 1); in clk_pll_recalc_rate()
/linux/include/linux/clk/
H A Danalogbits-wrpll-cln28hpc.h63 u16 divf; member
/linux/drivers/media/pci/solo6x10/
H A Dsolo6x10-core.c517 u32 divq, divf; in solo_pci_probe() local
523 divf = (solo_dev->clock_mhz * 4) / 3 - 1; in solo_pci_probe()
526 divf = (solo_dev->clock_mhz * 2) / 3 - 1; in solo_pci_probe()
533 (divf << 4) | in solo_pci_probe()
/linux/drivers/clk/sifive/
H A Dsifive-prci.c68 c->divf = v; in __prci_wrpll_unpack()
105 r |= c->divf << PRCI_COREPLLCFG0_DIVF_SHIFT; in __prci_wrpll_pack()