| /linux/drivers/clk/ |
| H A D | clk-loongson2.c | 38 u8 div_width; member
53 u8 div_width; member
67 .div_width = _dwidth, \
81 .div_width = _dwidth, \
93 .div_width = _dwidth, \
105 .div_width = _dwidth, \
289 div = loongson2_rate_part(val, clk->div_shift, clk->div_width); in loongson2_pll_recalc_rate()
306 scale = loongson2_rate_part(val, clk->div_shift, clk->div_width) + 1; in loongson2_freqscale_recalc_rate()
341 clk->div_width = cld->div_width; in loongson2_clk_register()
409 p->div_shift, p->div_width, in loongson2_clk_probe()
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| H A D | clk-sp7021.c | 47 int div_width; member
400 u32 max = 1 << clk->div_width; in sp_pll_calc_div()
417 } else if (clk->div_width == DIV_A) { in sp_pll_determine_rate()
419 } else if (clk->div_width == DIV_TV) { in sp_pll_determine_rate()
441 } else if (clk->div_width == DIV_A) { in sp_pll_recalc_rate()
443 } else if (clk->div_width == DIV_TV) { in sp_pll_recalc_rate()
469 u32 fbdiv = ((reg >> clk->div_shift) & ((1 << clk->div_width) - 1)) + 1; in sp_pll_recalc_rate()
488 } else if (clk->div_width == DIV_A) { in sp_pll_set_rate()
490 } else if (clk->div_width == DIV_TV) { in sp_pll_set_rate()
492 } else if (clk->div_width) { in sp_pll_set_rate()
[all …]
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| H A D | clk-bm1880.c | 121 s8 div_width; member
153 .div_width = _div_width, \
818 div_hws->div.width = clks->div_width; in bm1880_clk_register_composite()
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| H A D | clk-k210.c | 36 u8 div_width; member
56 .div_width = (_width), \
760 div_val = (reg >> cfg->div_shift) & GENMASK(cfg->div_width - 1, 0); in k210_clk_get_rate()
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| /linux/drivers/clk/rockchip/ |
| H A D | clk-ddr.c | 22 int div_width; member
95 int div_shift, int div_width, in rockchip_clk_register_ddrclk() argument
131 ddrclk->div_width = div_width; in rockchip_clk_register_ddrclk()
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| H A D | clk.h | 710 u8 div_width, u8 div_flags,
731 int div_shift, int div_width,
785 u8 div_width; member
810 .div_width = dw, \
832 .div_width = dw, \
850 .div_width = dw, \
868 .div_width = dw, \
908 .div_width = dw, \
927 .div_width = dw, \
943 .div_width = 16, \
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| H A D | clk.c | 44 int div_offset, u8 div_shift, u8 div_width, u8 div_flags, in rockchip_clk_register_branch() argument
86 if (div_width > 0) { in rockchip_clk_register_branch()
99 div->width = div_width; in rockchip_clk_register_branch()
556 list->div_shift, list->div_width, in rockchip_clk_register_branches()
563 list->div_shift, list->div_width, in rockchip_clk_register_branches()
581 list->div_width, list->div_flags, in rockchip_clk_register_branches()
607 list->div_shift, list->div_width, in rockchip_clk_register_branches()
641 list->div_shift, list->div_width, in rockchip_clk_register_branches()
651 list->div_width, list->div_flags, in rockchip_clk_register_branches()
737 list->div_width, list->div_flags, in rockchip_clk_register_armclk_multi_pll()
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| H A D | clk-half-divider.c | 165 u8 div_shift, u8 div_width, in rockchip_clk_register_halfdiv() argument
204 if (div_width > 0) { in rockchip_clk_register_halfdiv()
212 div->width = div_width; in rockchip_clk_register_halfdiv()
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| H A D | clk-cpu.c | 469 u8 div_width, u8 div_flags, in rockchip_clk_register_cpuclk_multi_pll() argument
495 if (div_width > 0) { in rockchip_clk_register_cpuclk_multi_pll()
508 div->width = div_width; in rockchip_clk_register_cpuclk_multi_pll()
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| /linux/drivers/clk/x86/ |
| H A D | clk-cgu.h | 183 u8 div_width; member
233 .div_width = _width, \
273 .div_width = _width, \
293 .div_width = _width, \
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| H A D | clk-cgu.c | 31 list->div_width, list->div_val); in lgm_clk_register_fixed()
201 u8 width = list->div_width; in lgm_clk_register_divider()
253 list->div_width, list->div_val); in lgm_clk_register_fixed_factor()
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| /linux/drivers/clk/socfpga/ |
| H A D | stratix10-clk.h | 70 u8 div_width; member
107 u8 div_width; member
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| H A D | clk-gate-s10.c | 152 socfpga_clk->width = clks->div_width; in s10_register_gate()
210 socfpga_clk->width = clks->div_width; in agilex_register_gate()
267 socfpga_clk->width = clks->div_width; in agilex5_register_gate()
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| /linux/drivers/clk/mediatek/ |
| H A D | clk-mtk.h | 212 unsigned char div_width; member
223 .div_width = _width, \
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| H A D | clk-mt8167-apmixedsys.c | 83 .div_width = _width, \
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| H A D | clk-mt8516.c | 475 .div_width = _width, \
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| H A D | clk-mt8167.c | 664 .div_width = _width, \
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| H A D | clk-mt8365.c | 548 .div_width = _width, \
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| H A D | clk-mtk.c | 419 mcd->div_width, mcd->clk_divider_flags, lock); in mtk_clk_register_dividers()
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