Home
last modified time | relevance | path

Searched refs:div_frc (Results 1 – 2 of 2) sorted by relevance

/linux/drivers/clk/
H A Dclk-versaclock5.c173 u32 div_frc; member
440 u32 div_int, div_frc; in vc5_pll_recalc_rate() local
446 div_frc = (fb[2] << 16) | (fb[3] << 8) | fb[4]; in vc5_pll_recalc_rate()
449 return (parent_rate * div_int) + ((parent_rate * div_frc) >> 24); in vc5_pll_recalc_rate()
458 u64 div_frc; in vc5_pll_determine_rate() local
468 div_frc = req->rate % req->best_parent_rate; in vc5_pll_determine_rate()
469 div_frc *= BIT(24) - 1; in vc5_pll_determine_rate()
470 do_div(div_frc, req->best_parent_rate); in vc5_pll_determine_rate()
473 hwdata->div_frc = (u32)div_frc; in vc5_pll_determine_rate()
475 req->rate = (req->best_parent_rate * div_int) + ((req->best_parent_rate * div_frc) >> 24); in vc5_pll_determine_rate()
[all …]
H A Dclk-versaclock3.c173 u32 div_frc; member
371 u32 div_int, div_frc, val; in vc3_pll_recalc_rate() local
381 div_frc = val << 8; in vc3_pll_recalc_rate()
383 div_frc |= val; in vc3_pll_recalc_rate()
385 (div_int * VC3_2_POW_16 + div_frc) / VC3_2_POW_16); in vc3_pll_recalc_rate()
398 u64 div_frc; in vc3_pll_determine_rate() local
412 div_frc = req->rate % req->best_parent_rate; in vc3_pll_determine_rate()
413 div_frc *= BIT(16) - 1; in vc3_pll_determine_rate()
415 vc3->div_frc = min_t(u64, in vc3_pll_determine_rate()
416 div64_ul(div_frc, req->best_parent_rate), in vc3_pll_determine_rate()
[all …]