Searched refs:div_clk (Results 1 – 5 of 5) sorted by relevance
138 struct clk_hw *div_clk; in visconti_clk_register_gates() local158 div_clk = devm_clk_hw_register_fixed_factor(dev, in visconti_clk_register_gates()163 if (IS_ERR(div_clk)) in visconti_clk_register_gates()164 return PTR_ERR(div_clk); in visconti_clk_register_gates()
173 struct clk *div_clk; member658 phy->div_clk = devm_clk_get(dev, "div-clk"); in ti_pipe3_get_clk()659 if (IS_ERR(phy->div_clk)) { in ti_pipe3_get_clk()661 return PTR_ERR(phy->div_clk); in ti_pipe3_get_clk()664 phy->div_clk = ERR_PTR(-ENODEV); in ti_pipe3_get_clk()882 if (!IS_ERR(phy->div_clk)) { in ti_pipe3_enable_clocks()883 ret = clk_prepare_enable(phy->div_clk); in ti_pipe3_enable_clocks()909 if (!IS_ERR(phy->div_clk)) in ti_pipe3_disable_clocks()910 clk_disable_unprepare(phy->div_clk); in ti_pipe3_disable_clocks()
669 static struct clk_hw *bm1880_clk_register_div(struct bm1880_div_hw_clock *div_clk, in bm1880_clk_register_div() argument675 div_clk->div.flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO; in bm1880_clk_register_div()676 div_clk->base = sys_base; in bm1880_clk_register_div()677 div_clk->lock = &bm1880_clk_lock; in bm1880_clk_register_div()679 hw = &div_clk->hw; in bm1880_clk_register_div()
1002 int div_clk; in calc_core_pll_rate() local1004 for (div_clk = 1; div_clk <= 256; div_clk++) { in calc_core_pll_rate()1005 core_rate = target_rate * div_clk * div_prim; in calc_core_pll_rate()1010 best_div_clk = div_clk; in calc_core_pll_rate()1058 int div_prim, div_clk; in rp1_clock_choose_div_and_prate() local1060 core_rate = calc_core_pll_rate(parent, rate, &div_prim, &div_clk); in rp1_clock_choose_div_and_prate()1062 i2s_rate = DIV_ROUND_CLOSEST(audio_rate, div_clk); in rp1_clock_choose_div_and_prate()
205 struct clk *div_clk; member