| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/ |
| H A D | dml2_core_dcn5_funcs_mode_programming.c | 13 const struct dml2_display_cfg *display_cfg = in_out_params->in_display_cfg; in dcn5_mode_programming() local
41 s->num_active_planes = display_cfg->num_planes; in dcn5_mode_programming()
42 dml2_core_utils_get_stream_output_bpp(s->OutputBpp, display_cfg); in dcn5_mode_programming()
44 …mode_lib->mp.num_active_pipes = dml2_core_util_get_num_active_pipes(display_cfg->num_planes, cfg_s… in dcn5_mode_programming()
53 unsigned int stream_index = display_cfg->plane_descriptors[k].stream_index; in dcn5_mode_programming()
90 unsigned int stream_index = display_cfg->plane_descriptors[k].stream_index; in dcn5_mode_programming()
128 …DML_LOG_VERBOSE("DML::%s: plane_%d: reserved_vblank_time_ns = %lu\n", __func__, k, display_cfg->pl… in dcn5_mode_programming()
135 display_cfg->overrides.hw.force_nom_det_size_kbytes.enable, in dcn5_mode_programming()
136 display_cfg->overrides.hw.force_nom_det_size_kbytes.value, in dcn5_mode_programming()
145 …dcn5_adjust_pixel_clock_for_progressive_to_interlace_unit(display_cfg, mode_lib->ip.ptoi_supported… in dcn5_mode_programming()
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| H A D | dml2_core_dcn6_calcs_dchub.c | 55 for (i = 0; i < p->display_cfg->num_streams; i++) { in dcn6_calculate_alternate_svp_lines()
56 …line_time_us = ((double)p->display_cfg->stream_descriptors[i].timing.h_total * 1000 / p->display_c… in dcn6_calculate_alternate_svp_lines()
57 for (j = 0; j < p->display_cfg->num_planes; j++) { in dcn6_calculate_alternate_svp_lines()
58 if (p->display_cfg->plane_descriptors[j].stream_index == i) { in dcn6_calculate_alternate_svp_lines()
59 vratio = p->display_cfg->plane_descriptors[j].composition.scaler_info.plane0.v_ratio; in dcn6_calculate_alternate_svp_lines()
60 vratio_c = p->display_cfg->plane_descriptors[j].composition.scaler_info.plane1.v_ratio; in dcn6_calculate_alternate_svp_lines()
76 for (i = 0; i < p->display_cfg->num_streams; i++) { in dcn6_calculate_alternate_svp_lines()
77 …line_time_us = ((double)p->display_cfg->stream_descriptors[i].timing.h_total * 1000 / p->display_c… in dcn6_calculate_alternate_svp_lines()
109 const struct dml2_plane_parameters *plane = &p->display_cfg->plane_descriptors[plane_idx]; in get_plane_params()
110 …l vertical_access = p->display_cfg->plane_descriptors[plane_idx].composition.rotation_angle == dml… in get_plane_params()
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| H A D | dml2_core_dcn5_calcs_dchub.c | 246 const struct dml2_display_cfg *display_cfg, in dcn5_calculate_swath_width() argument
288 …if (!dml2_core_utils_is_vertical_rotation(display_cfg->plane_descriptors[k].composition.rotation_a… in dcn5_calculate_swath_width()
289 …SwathWidthSingleDPPY[k] = (unsigned int)display_cfg->plane_descriptors[k].composition.viewport.pla… in dcn5_calculate_swath_width()
291 …SwathWidthSingleDPPY[k] = (unsigned int)display_cfg->plane_descriptors[k].composition.viewport.pla… in dcn5_calculate_swath_width()
294 …DML_LOG_VERBOSE("DML::%s: k=%u ViewportWidth=%lu\n", __func__, k, display_cfg->plane_descriptors[k… in dcn5_calculate_swath_width()
295 …DML_LOG_VERBOSE("DML::%s: k=%u ViewportHeight=%lu\n", __func__, k, display_cfg->plane_descriptors[… in dcn5_calculate_swath_width()
311 …nd((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.… in dcn5_calculate_swath_width()
319 …OG_VERBOSE("DML::%s: k=%u HActive=%lu\n", __func__, k, display_cfg->stream_descriptors[display_cfg… in dcn5_calculate_swath_width()
320 …DML_LOG_VERBOSE("DML::%s: k=%u HRatio=%f\n", __func__, k, display_cfg->plane_descriptors[k].compos… in dcn5_calculate_swath_width()
325 …if (dml2_core_utils_is_420(display_cfg->plane_descriptors[k].pixel_format) || dml2_core_utils_is_4… in dcn5_calculate_swath_width()
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| H A D | dml2_core_utils.c | 337 … dml2_core_utils_get_stream_output_bpp(double *out_bpp, const struct dml2_display_cfg *display_cfg) in dml2_core_utils_get_stream_output_bpp() argument
339 for (unsigned int k = 0; k < display_cfg->num_planes; k++) { in dml2_core_utils_get_stream_output_bpp()
340 …double bpc = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_inde… in dml2_core_utils_get_stream_output_bpp()
341 …if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.ena… in dml2_core_utils_get_stream_output_bpp()
342 …switch (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.out… in dml2_core_utils_get_stream_output_bpp()
357 …} else if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.… in dml2_core_utils_get_stream_output_bpp()
358 …out_bpp[k] = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_inde… in dml2_core_utils_get_stream_output_bpp()
364 …_VERBOSE("DML::%s: k=%d dsc.enable=%d\n", __func__, k, display_cfg->stream_descriptors[display_cfg… in dml2_core_utils_get_stream_output_bpp()
610 void dml2_core_utils_expand_implict_subvp(const struct display_configuation_with_meta *display_cfg,… in dml2_core_utils_expand_implict_subvp() argument
618 memcpy(svp_expanded_display_cfg, &display_cfg->display_config, sizeof(struct dml2_display_cfg)); in dml2_core_utils_expand_implict_subvp()
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| H A D | dml2_core_utils.h | 18 …dml2_core_utils_get_stream_output_bpp(double *out_bpp, const struct dml2_display_cfg *display_cfg);
32 void dml2_core_utils_expand_implict_subvp(const struct display_configuation_with_meta *display_cfg,…
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| H A D | dml2_core_shared_types.h | 1385 const struct dml2_display_cfg *display_cfg; member
1511 const struct dml2_display_cfg *display_cfg; member
1739 const struct dml2_display_cfg *display_cfg; member
1793 const struct dml2_display_cfg *display_cfg; member
1847 const struct dml2_display_cfg *display_cfg; member
1938 const struct dml2_display_cfg *display_cfg; member
1995 const struct dml2_display_cfg *display_cfg; member
2255 const struct dml2_display_cfg *display_cfg; member
2265 const struct dml2_display_cfg *display_cfg; member
2280 const struct dml2_display_cfg *display_cfg; member
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/ |
| H A D | dml2_pmo_dcn6_stage_optimizers.c | 71 static bool all_planes_match_method(const struct dml2_display_cfg *display_cfg, int plane_mask, enu… in all_planes_match_method() argument
77 …if (display_cfg->plane_descriptors[i].overrides.uclk_pstate_change_strategy != dml2_uclk_pstate_ch… in all_planes_match_method()
78 …display_cfg->plane_descriptors[i].overrides.uclk_pstate_change_strategy != pstate_method_to_uclk_p… in all_planes_match_method()
167 const struct dml2_display_cfg *display_cfg, in dcn6_is_timing_group_schedulable() argument
179 for (base_stream_idx = 0; base_stream_idx < display_cfg->num_streams; base_stream_idx++) { in dcn6_is_timing_group_schedulable()
194 for (i = base_stream_idx + 1; i < display_cfg->num_streams; i++) { in dcn6_is_timing_group_schedulable()
227 const struct dml2_display_cfg *display_cfg, in dcn6_is_pstate_schedulable() argument
243 if (display_cfg->num_streams == 0) { in dcn6_is_pstate_schedulable()
253 display_cfg, in dcn6_is_pstate_schedulable()
605 const struct dml2_display_cfg *display_cfg, in validate_pstate_support_strategy_cofunctionality() argument
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | dml2_wrapper_fpu.c | 98 const struct dml_display_cfg_st *display_cfg, in pack_and_call_dml_mode_support_ex() argument
105 s->mode_support_params.in_display_cfg = display_cfg; in pack_and_call_dml_mode_support_ex()
238 static bool are_timings_requiring_odm_doing_blending(const struct dml_display_cfg_st *display_cfg, in are_timings_requiring_odm_doing_blending() argument
244 for (i = 0; i < display_cfg->num_surfaces; i++) in are_timings_requiring_odm_doing_blending()
245 planes_per_timing[display_cfg->plane.BlendingAndTiming[i]]++; in are_timings_requiring_odm_doing_blending()
255 …figuration_meet_sw_policies(struct dml2_context *ctx, const struct dml_display_cfg_st *display_cfg, in does_configuration_meet_sw_policies() argument
261 if (are_timings_requiring_odm_doing_blending(display_cfg, evaluation_info)) in does_configuration_meet_sw_policies()
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| /linux/drivers/gpu/drm/amd/pm/legacy-dpm/ |
| H A D | si_dpm.c | 3445 const struct amd_pp_display_configuration *display_cfg = in si_apply_state_adjust_rules() local
3499 for (i = 0; i < display_cfg->num_display; i++) { in si_apply_state_adjust_rules()
3501 if (display_cfg->displays[i].pixel_clock > 297000) in si_apply_state_adjust_rules()
3682 display_cfg->display_clk, in si_apply_state_adjust_rules()
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