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Searched refs:display_cfg (Results 1 – 17 of 17) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/
H A Ddml2_core_shared.c26 static void get_stream_output_bpp(double *out_bpp, const struct dml2_display_cfg *display_cfg);
31 static bool dml_get_is_phantom_pipe(const struct dml2_display_cfg *display_cfg, const struct dml2_c…
44 …AdjustmentForProgressiveToInterlaceUnit(const struct dml2_display_cfg *display_cfg, bool ptoi_supp…
87 const struct dml2_display_cfg *display_cfg,
185 const struct dml2_display_cfg *display_cfg,
227 const struct dml2_display_cfg *display_cfg,
256 const struct dml2_display_cfg *display_cfg,
339 const struct dml2_display_cfg *display_cfg,
450 const struct dml2_display_cfg *display_cfg,
469 const struct dml2_display_cfg *display_cfg,
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H A Ddml2_core_utils.c191 … dml2_core_utils_get_stream_output_bpp(double *out_bpp, const struct dml2_display_cfg *display_cfg) in dml2_core_utils_get_stream_output_bpp() argument
193 for (unsigned int k = 0; k < display_cfg->num_planes; k++) { in dml2_core_utils_get_stream_output_bpp()
194 …double bpc = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_inde… in dml2_core_utils_get_stream_output_bpp()
195 …if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.ena… in dml2_core_utils_get_stream_output_bpp()
196 …switch (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.out… in dml2_core_utils_get_stream_output_bpp()
211 …} else if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.… in dml2_core_utils_get_stream_output_bpp()
212 …out_bpp[k] = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_inde… in dml2_core_utils_get_stream_output_bpp()
218 …2_printf("DML::%s: k=%d dsc.enable=%d\n", __func__, k, display_cfg->stream_descriptors[display_cfg… in dml2_core_utils_get_stream_output_bpp()
454 void dml2_core_utils_expand_implict_subvp(const struct display_configuation_with_meta *display_cfg,… in dml2_core_utils_expand_implict_subvp() argument
462 memcpy(svp_expanded_display_cfg, &display_cfg->display_config, sizeof(struct dml2_display_cfg)); in dml2_core_utils_expand_implict_subvp()
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H A Ddml2_core_dcn4_calcs.h21 void dml2_core_calcs_get_watermarks(const struct dml2_display_cfg *display_cfg, const struct dml2_c…
22 void dml2_core_calcs_get_arb_params(const struct dml2_display_cfg *display_cfg, const struct dml2_c…
27 void dml2_core_calcs_get_plane_support_info(const struct dml2_display_cfg *display_cfg, const struc…
29 void dml2_core_calcs_get_stream_support_info(const struct dml2_display_cfg *display_cfg, const stru…
31 …splay_mode_lib *mode_lib, const struct display_configuation_with_meta *display_cfg, struct dmub_fa…
32 …splay_mode_lib *mode_lib, const struct display_configuation_with_meta *display_cfg, struct dmub_cm…
H A Ddml2_core_dcn4.c188 static void expand_implict_subvp(const struct display_configuation_with_meta *display_cfg, struct d… in expand_implict_subvp() argument
196 memcpy(svp_expanded_display_cfg, &display_cfg->display_config, sizeof(struct dml2_display_cfg)); in expand_implict_subvp()
201 if (!display_cfg->display_config.overrides.enable_subvp_implicit_pmo) in expand_implict_subvp()
205 if (!display_cfg->stage3.performed) { in expand_implict_subvp()
210 for (stream_index = 0; stream_index < display_cfg->display_config.num_streams; stream_index++) { in expand_implict_subvp()
211 main_stream = &display_cfg->display_config.stream_descriptors[stream_index]; in expand_implict_subvp()
215 if (display_cfg->stage3.stream_svp_meta[stream_index].valid) { in expand_implict_subvp()
218 main_stream, &display_cfg->stage3.stream_svp_meta[stream_index]); in expand_implict_subvp()
230 for (plane_index = 0; plane_index < display_cfg->display_config.num_planes; plane_index++) { in expand_implict_subvp()
231 main_plane = &display_cfg->display_config.plane_descriptors[plane_index]; in expand_implict_subvp()
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H A Ddml2_core_utils.h16 …dml2_core_utils_get_stream_output_bpp(double *out_bpp, const struct dml2_display_cfg *display_cfg);
28 void dml2_core_utils_expand_implict_subvp(const struct display_configuation_with_meta *display_cfg,…
H A Ddml2_core_shared_types.h1104 const struct dml2_display_cfg *display_cfg; member
1234 const struct dml2_display_cfg *display_cfg; member
1458 const struct dml2_display_cfg *display_cfg; member
1512 const struct dml2_display_cfg *display_cfg; member
1563 const struct dml2_display_cfg *display_cfg; member
1649 const struct dml2_display_cfg *display_cfg; member
1701 const struct dml2_display_cfg *display_cfg; member
1937 const struct dml2_display_cfg *display_cfg; member
1969 const struct dml2_display_cfg *display_cfg; member
/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/
H A Ddml2_dpmm_dcn4.c29 if (in_out->display_cfg->stage3.success) in get_minimum_clocks_for_latency()
30 min_clock_index_for_latency = in_out->display_cfg->stage3.min_clk_index_for_latency; in get_minimum_clocks_for_latency()
32 min_clock_index_for_latency = in_out->display_cfg->stage1.min_clk_index_for_latency; in get_minimum_clocks_for_latency()
54 …const struct dml2_core_mode_support_result *mode_support_result = &in_out->display_cfg->mode_suppo… in calculate_system_active_minimums()
60 if (in_out->display_cfg->display_config.hostvm_enable) in calculate_system_active_minimums()
97 …const struct dml2_core_mode_support_result *mode_support_result = &in_out->display_cfg->mode_suppo… in calculate_svp_prefetch_minimums()
136 …const struct dml2_core_mode_support_result *mode_support_result = &in_out->display_cfg->mode_suppo… in calculate_idle_minimums()
251 static bool map_soc_min_clocks_to_dpm_fine_grained(struct dml2_display_cfg_programming *display_cfg… in map_soc_min_clocks_to_dpm_fine_grained() argument
255 …result = round_up_to_next_dpm(&display_cfg->min_clocks.dcn4x.active.dcfclk_khz, &state_table->dcfc… in map_soc_min_clocks_to_dpm_fine_grained()
257 result = round_up_to_next_dpm(&display_cfg->min_clocks.dcn4x.active.fclk_khz, &state_table->fclk); in map_soc_min_clocks_to_dpm_fine_grained()
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/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/
H A Ddml2_pmo_dcn4_fams2.c231 static int count_planes_with_stream_index(const struct dml2_display_cfg *display_cfg, unsigned int … in count_planes_with_stream_index() argument
236 for (i = 0; i < display_cfg->num_planes; i++) { in count_planes_with_stream_index()
237 if (display_cfg->plane_descriptors[i].stream_index == stream_index) in count_planes_with_stream_index()
1109 static bool all_planes_match_method(const struct display_configuation_with_meta *display_cfg, int p… in all_planes_match_method() argument
1125 …if (display_cfg->display_config.plane_descriptors[i].overrides.uclk_pstate_change_strategy != dml2… in all_planes_match_method()
1126 …display_cfg->display_config.plane_descriptors[i].overrides.uclk_pstate_change_strategy != matching… in all_planes_match_method()
1187 const struct display_configuation_with_meta *display_cfg, in is_timing_group_schedulable() argument
1199 …for (base_stream_idx = 0; base_stream_idx < display_cfg->display_config.num_streams; base_stream_i… in is_timing_group_schedulable()
1214 for (i = base_stream_idx + 1; i < display_cfg->display_config.num_streams; i++) { in is_timing_group_schedulable()
1247 const struct display_configuation_with_meta *display_cfg, in is_config_schedulable() argument
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H A Ddml2_pmo_dcn3.c183 static int count_planes_with_stream_index(const struct dml2_display_cfg *display_cfg, unsigned int … in count_planes_with_stream_index() argument
188 for (i = 0; i < display_cfg->num_planes; i++) { in count_planes_with_stream_index()
189 if (display_cfg->plane_descriptors[i].stream_index == stream_index) in count_planes_with_stream_index()
/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/
H A Ddml_top.c109 l->mode_support_params.display_cfg = &l->base_display_config_with_meta; in dml2_check_mode_supported()
133 l->dppm_map_mode_params.display_cfg = &l->base_display_config_with_meta; in dml2_check_mode_supported()
166 l->mode_support_params.display_cfg = &l->base_display_config_with_meta; in dml2_build_mode_programming()
177 l->mode_support_params.display_cfg = &l->base_display_config_with_meta; in dml2_build_mode_programming()
314 l->dppm_map_mode_params.display_cfg = &l->base_display_config_with_meta; in dml2_build_mode_programming()
325 l->mode_programming_params.display_cfg = &l->base_display_config_with_meta; in dml2_build_mode_programming()
336 l->dppm_map_watermarks_params.display_cfg = &l->base_display_config_with_meta; in dml2_build_mode_programming()
H A Ddml2_top_optimization.c64 …l->test_mcache.validate_admissibility_params.display_cfg = &params->display_config->display_config; in dml2_top_optimization_test_function_mcache()
173 l->mode_support_params.display_cfg = &l->next_candidate_display_cfg; in dml2_top_optimization_perform_optimization_phase()
227 l->mode_support_params.display_cfg = &l->cur_candidate_display_cfg; in dml2_top_optimization_perform_optimization_phase_1()
H A Ddml_top_mcache.c222 for (plane_index = 0; plane_index < params->display_cfg->num_planes; plane_index++) { in dml2_top_mcache_validate_admissability()
223 if (!params->display_cfg->plane_descriptors[plane_index].surface.dcc.enable) in dml2_top_mcache_validate_admissability()
226 plane = &params->display_cfg->plane_descriptors[plane_index]; in dml2_top_mcache_validate_admissability()
227 stream = &params->display_cfg->stream_descriptors[plane->stream_index]; in dml2_top_mcache_validate_admissability()
/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/inc/
H A Ddml2_internal_shared_types.h83 const struct display_configuation_with_meta *display_cfg; member
100 const struct display_configuation_with_meta *display_cfg; member
364 const struct display_configuation_with_meta *display_cfg; member
376 struct dml_display_cfg_st *display_cfg; member
396 const struct display_configuation_with_meta *display_cfg; member
759 const struct dml2_display_cfg *display_cfg; member
/linux/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddisplay_mode_util.h69 …ML_DLL_EXPORT__ dml_uint_t dml_get_num_active_planes(const struct dml_display_cfg_st *display_cfg);
70 __DML_DLL_EXPORT__ dml_uint_t dml_get_num_active_pipes(const struct dml_display_cfg_st *display_cfg…
H A Ddml2_wrapper.c95 const struct dml_display_cfg_st *display_cfg, in pack_and_call_dml_mode_support_ex() argument
101 s->mode_support_params.in_display_cfg = display_cfg; in pack_and_call_dml_mode_support_ex()
303 static bool are_timings_requiring_odm_doing_blending(const struct dml_display_cfg_st *display_cfg, in are_timings_requiring_odm_doing_blending() argument
309 for (i = 0; i < display_cfg->num_surfaces; i++) in are_timings_requiring_odm_doing_blending()
310 planes_per_timing[display_cfg->plane.BlendingAndTiming[i]]++; in are_timings_requiring_odm_doing_blending()
320 …figuration_meet_sw_policies(struct dml2_context *ctx, const struct dml_display_cfg_st *display_cfg, in does_configuration_meet_sw_policies() argument
326 if (are_timings_requiring_odm_doing_blending(display_cfg, evaluation_info)) in does_configuration_meet_sw_policies()
H A Ddisplay_mode_core.h67 const struct dml_display_cfg_st *display_cfg);
72 const struct dml_display_cfg_st *display_cfg,
H A Ddisplay_mode_util.c728 dml_uint_t dml_get_num_active_planes(const struct dml_display_cfg_st *display_cfg) in dml_get_num_active_planes() argument
733 if (display_cfg->plane.ViewportWidth[k] > 0) in dml_get_num_active_planes()
743 dml_uint_t dml_get_num_active_pipes(const struct dml_display_cfg_st *display_cfg) in dml_get_num_active_pipes() argument
747 for (dml_uint_t j = 0; j < dml_get_num_active_planes(display_cfg); j++) { in dml_get_num_active_pipes()
748 num_active_pipes = num_active_pipes + display_cfg->hw.DPPPerSurface[j]; in dml_get_num_active_pipes()