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Searched refs:display_cfg (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/
H A Ddml2_core_dcn4_calcs.c158 static void get_stream_output_bpp(double *out_bpp, const struct dml2_display_cfg *display_cfg) in get_stream_output_bpp()
160 for (unsigned int k = 0; k < display_cfg->num_planes; k++) { in get_stream_output_bpp()
161 double bpc = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.bpc; in get_stream_output_bpp()
162 if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_disable) { in get_stream_output_bpp()
163 switch (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format) { in get_stream_output_bpp()
178 } else if (display_cfg->stream_descriptors[display_cfg in get_stream_output_bpp()
157 get_stream_output_bpp(double * out_bpp,const struct dml2_display_cfg * display_cfg) get_stream_output_bpp() argument
245 dml_get_is_phantom_pipe(const struct dml2_display_cfg * display_cfg,const struct dml2_core_internal_display_mode_lib * mode_lib,unsigned int pipe_idx) dml_get_is_phantom_pipe() argument
429 PixelClockAdjustmentForProgressiveToInterlaceUnit(const struct dml2_display_cfg * display_cfg,bool ptoi_supported,double * PixelClockBackEnd) PixelClockAdjustmentForProgressiveToInterlaceUnit() argument
817 CalculateSwathWidth(const struct dml2_display_cfg * display_cfg,bool ForceSingleDPP,unsigned int NumberOfActiveSurfaces,enum dml2_odm_mode ODMMode[],unsigned int BytePerPixY[],unsigned int BytePerPixC[],unsigned int Read256BytesBlockHeightY[],unsigned int Read256BytesBlockHeightC[],unsigned int Read256BytesBlockWidthY[],unsigned int Read256BytesBlockWidthC[],bool surf_linear128_l[],bool surf_linear128_c[],unsigned int DPPPerSurface[],unsigned int req_per_swath_ub_l[],unsigned int req_per_swath_ub_c[],unsigned int SwathWidthSingleDPPY[],unsigned int SwathWidthSingleDPPC[],unsigned int SwathWidthY[],unsigned int SwathWidthC[],unsigned int MaximumSwathHeightY[],unsigned int MaximumSwathHeightC[],unsigned int swath_width_luma_ub[],unsigned int swath_width_chroma_ub[]) CalculateSwathWidth() argument
1009 CalculateDETBufferSize(struct dml2_core_shared_CalculateDETBufferSize_locals * l,const struct dml2_display_cfg * display_cfg,bool ForceSingleDPP,unsigned int NumberOfActiveSurfaces,bool UnboundedRequestEnabled,unsigned int nomDETInKByte,unsigned int MaxTotalDETInKByte,unsigned int ConfigReturnBufferSizeInKByte,unsigned int MinCompressedBufferSizeInKByte,unsigned int ConfigReturnBufferSegmentSizeInkByte,unsigned int CompressedBufferSegmentSizeInkByte,double ReadBandwidthLuma[],double ReadBandwidthChroma[],unsigned int full_swath_bytes_l[],unsigned int full_swath_bytes_c[],unsigned int DPPPerSurface[],unsigned int DETBufferSizeInKByte[],unsigned int * CompressedBufferSizeInkByte) CalculateDETBufferSize() argument
1949 CalculateMALLUseForStaticScreen(const struct dml2_display_cfg * display_cfg,unsigned int NumberOfActiveSurfaces,unsigned int MALLAllocatedForDCN,unsigned int SurfaceSizeInMALL[],bool one_row_per_frame_fits_in_buffer[],bool is_using_mall_for_ss[]) CalculateMALLUseForStaticScreen() argument
2644 calculate_mall_bw_overhead_factor(double mall_prefetch_sdp_overhead_factor[],double mall_prefetch_dram_overhead_factor[],const struct dml2_display_cfg * display_cfg,unsigned int num_active_planes) calculate_mall_bw_overhead_factor() argument
2820 calculate_avg_bandwidth_required(double avg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max],const struct dml2_display_cfg * display_cfg,unsigned int num_active_planes,double ReadBandwidthLuma[],double ReadBandwidthChroma[],double cursor_bw[],double dcc_dram_bw_nom_overhead_factor_p0[],double dcc_dram_bw_nom_overhead_factor_p1[],double mall_prefetch_dram_overhead_factor[],double mall_prefetch_sdp_overhead_factor[]) calculate_avg_bandwidth_required() argument
3505 CalculateDCFCLKDeepSleepTdlut(const struct dml2_display_cfg * display_cfg,unsigned int NumberOfActiveSurfaces,unsigned int BytePerPixelY[],unsigned int BytePerPixelC[],unsigned int SwathWidthY[],unsigned int SwathWidthC[],unsigned int DPPPerSurface[],double PSCL_THROUGHPUT[],double PSCL_THROUGHPUT_CHROMA[],double Dppclk[],double ReadBandwidthLuma[],double ReadBandwidthChroma[],unsigned int ReturnBusWidth,double dispclk,unsigned int tdlut_bytes_to_deliver[],double prefetch_swath_time_us[],double * DCFClkDeepSleep) CalculateDCFCLKDeepSleepTdlut() argument
3600 CalculateDCFCLKDeepSleep(const struct dml2_display_cfg * display_cfg,unsigned int NumberOfActiveSurfaces,unsigned int BytePerPixelY[],unsigned int BytePerPixelC[],unsigned int SwathWidthY[],unsigned int SwathWidthC[],unsigned int DPPPerSurface[],double PSCL_THROUGHPUT[],double PSCL_THROUGHPUT_CHROMA[],double Dppclk[],double ReadBandwidthLuma[],double ReadBandwidthChroma[],unsigned int ReturnBusWidth,double * DCFClkDeepSleep) CalculateDCFCLKDeepSleep() argument
4561 CalculateSurfaceSizeInMall(const struct dml2_display_cfg * display_cfg,unsigned int NumberOfActiveSurfaces,unsigned int MALLAllocatedForDCN,unsigned int BytesPerPixelY[],unsigned int BytesPerPixelC[],unsigned int Read256BytesBlockWidthY[],unsigned int Read256BytesBlockWidthC[],unsigned int Read256BytesBlockHeightY[],unsigned int Read256BytesBlockHeightC[],unsigned int ReadBlockWidthY[],unsigned int ReadBlockWidthC[],unsigned int ReadBlockHeightY[],unsigned int ReadBlockHeightC[],unsigned int SurfaceSizeInMALL[],bool * ExceededMALLSize) CalculateSurfaceSizeInMall() argument
4759 CalculateTarb(const struct dml2_display_cfg * display_cfg,unsigned int PixelChunkSizeInKByte,unsigned int NumberOfActiveSurfaces,unsigned int NumberOfDPP[],unsigned int dpte_group_bytes[],unsigned int tdlut_bytes_per_group[],double HostVMInefficiencyFactor,double HostVMInefficiencyFactorPrefetch,unsigned int HostVMMinPageSize,double ReturnBW,unsigned int MetaChunkSize,double * Tarb,double * Tarb_prefetch) CalculateTarb() argument
4886 get_urgent_bandwidth_required(struct dml2_core_shared_get_urgent_bandwidth_required_locals * l,const struct dml2_display_cfg * display_cfg,enum dml2_core_internal_soc_state_type state_type,enum dml2_core_internal_bw_type bw_type,bool inc_flip_bw,bool use_qual_row_bw,unsigned int NumberOfActiveSurfaces,unsigned int NumberOfDPP[],double dcc_dram_bw_nom_overhead_factor_p0[],double dcc_dram_bw_nom_overhead_factor_p1[],double dcc_dram_bw_pref_overhead_factor_p0[],double dcc_dram_bw_pref_overhead_factor_p1[],double mall_prefetch_sdp_overhead_factor[],double mall_prefetch_dram_overhead_factor[],double ReadBandwidthLuma[],double ReadBandwidthChroma[],double PrefetchBandwidthLuma[],double PrefetchBandwidthChroma[],double PrefetchBandwidthMax[],double excess_vactive_fill_bw_l[],double excess_vactive_fill_bw_c[],double cursor_bw[],double dpte_row_bw[],double meta_row_bw[],double prefetch_cursor_bw[],double prefetch_vmrow_bw[],double flip_bw[],double UrgentBurstFactorLuma[],double UrgentBurstFactorChroma[],double UrgentBurstFactorCursor[],double UrgentBurstFactorLumaPre[],double UrgentBurstFactorChromaPre[],double UrgentBurstFactorCursorPre[],double surface_required_bw[],double surface_peak_required_bw[]) get_urgent_bandwidth_required() argument
5024 CalculateExtraLatency(const struct dml2_display_cfg * display_cfg,unsigned int ROBBufferSizeInKByte,unsigned int RoundTripPingLatencyCycles,unsigned int ReorderingBytes,double DCFCLK,double FabricClock,unsigned int PixelChunkSizeInKByte,double ReturnBW,unsigned int NumberOfActiveSurfaces,unsigned int NumberOfDPP[],unsigned int dpte_group_bytes[],unsigned int tdlut_bytes_per_group[],double HostVMInefficiencyFactor,double HostVMInefficiencyFactorPrefetch,unsigned int HostVMMinPageSize,enum dml2_qos_param_type qos_type,bool max_outstanding_when_urgent_expected,unsigned int max_outstanding_requests,unsigned int request_size_bytes_luma[],unsigned int request_size_bytes_chroma[],unsigned int MetaChunkSize,unsigned int dchub_arb_to_ret_delay,double Ttrip,unsigned int hostvm_mode,double * ExtraLatency,double * ExtraLatency_sr,double * ExtraLatencyPrefetch) CalculateExtraLatency() argument
7026 calculate_vactive_det_fill_latency(const struct dml2_display_cfg * display_cfg,unsigned int num_active_planes,unsigned int bytes_required_l[],unsigned int bytes_required_c[],double dcc_dram_bw_nom_overhead_factor_p0[],double dcc_dram_bw_nom_overhead_factor_p1[],double surface_read_bw_l[],double surface_read_bw_c[],double (* surface_avg_vactive_required_bw)[dml2_core_internal_bw_max][DML2_MAX_PLANES],double (* surface_peak_required_bw)[dml2_core_internal_bw_max][DML2_MAX_PLANES],double vactive_det_fill_delay_us[]) calculate_vactive_det_fill_latency() argument
7077 calculate_excess_vactive_bandwidth_required(const struct dml2_display_cfg * display_cfg,unsigned int num_active_planes,unsigned int bytes_required_l[],unsigned int bytes_required_c[],double excess_vactive_fill_bw_l[],double excess_vactive_fill_bw_c[]) calculate_excess_vactive_bandwidth_required() argument
7306 calculate_pstate_keepout_dst_lines(const struct dml2_display_cfg * display_cfg,const struct dml2_core_internal_watermarks * watermarks,unsigned int pstate_keepout_dst_lines[]) calculate_pstate_keepout_dst_lines() argument
7328 dml_core_ms_prefetch_check(struct dml2_core_internal_display_mode_lib * mode_lib,const struct dml2_display_cfg * display_cfg) dml_core_ms_prefetch_check() argument
7971 const struct dml2_display_cfg *display_cfg = in_out_params->in_display_cfg; dml_core_mode_support() local
9668 CalculatePixelDeliveryTimes(const struct dml2_display_cfg * display_cfg,const struct core_display_cfg_support_info * cfg_support_info,unsigned int NumberOfActiveSurfaces,double VRatioPrefetchY[],double VRatioPrefetchC[],unsigned int swath_width_luma_ub[],unsigned int swath_width_chroma_ub[],double PSCL_THROUGHPUT[],double PSCL_THROUGHPUT_CHROMA[],double Dppclk[],unsigned int BytePerPixelC[],unsigned int req_per_swath_ub_l[],unsigned int req_per_swath_ub_c[],double DisplayPipeLineDeliveryTimeLuma[],double DisplayPipeLineDeliveryTimeChroma[],double DisplayPipeLineDeliveryTimeLumaPrefetch[],double DisplayPipeLineDeliveryTimeChromaPrefetch[],double DisplayPipeRequestDeliveryTimeLuma[],double DisplayPipeRequestDeliveryTimeChroma[],double DisplayPipeRequestDeliveryTimeLumaPrefetch[],double DisplayPipeRequestDeliveryTimeChromaPrefetch[]) CalculatePixelDeliveryTimes() argument
9970 CalculateVMGroupAndRequestTimes(const struct dml2_display_cfg * display_cfg,unsigned int NumberOfActiveSurfaces,unsigned int BytePerPixelC[],double dst_y_per_vm_vblank[],double dst_y_per_vm_flip[],unsigned int dpte_row_width_luma_ub[],unsigned int dpte_row_width_chroma_ub[],unsigned int vm_group_bytes[],unsigned int dpde0_bytes_per_frame_ub_l[],unsigned int dpde0_bytes_per_frame_ub_c[],unsigned int tdlut_pte_bytes_per_frame[],unsigned int meta_pte_bytes_per_frame_ub_l[],unsigned int meta_pte_bytes_per_frame_ub_c[],bool mrq_present,double TimePerVMGroupVBlank[],double TimePerVMGroupFlip[],double TimePerVMRequestVBlank[],double TimePerVMRequestFlip[]) CalculateVMGroupAndRequestTimes() argument
10404 const struct dml2_display_cfg *display_cfg = in_out_params->in_display_cfg; dml_core_mode_programming() local
12225 rq_dlg_get_wm_regs(const struct dml2_display_cfg * display_cfg,const struct dml2_core_internal_display_mode_lib * mode_lib,struct dml2_dchub_watermark_regs * wm_regs) rq_dlg_get_wm_regs() argument
12275 rq_dlg_get_rq_reg(struct dml2_display_rq_regs * rq_regs,const struct dml2_display_cfg * display_cfg,const struct dml2_core_internal_display_mode_lib * mode_lib,unsigned int pipe_idx) rq_dlg_get_rq_reg() argument
12439 rq_dlg_get_dlg_reg(struct dml2_core_internal_scratch * s,struct dml2_display_dlg_regs * disp_dlg_regs,struct dml2_display_ttu_regs * disp_ttu_regs,const struct dml2_display_cfg * display_cfg,const struct dml2_core_internal_display_mode_lib * mode_lib,const unsigned int pipe_idx) rq_dlg_get_dlg_reg() argument
12754 rq_dlg_get_arb_params(const struct dml2_display_cfg * display_cfg,const struct dml2_core_internal_display_mode_lib * mode_lib,struct dml2_display_arb_regs * arb_param) rq_dlg_get_arb_params() argument
12781 dml2_core_calcs_get_watermarks(const struct dml2_display_cfg * display_cfg,const struct dml2_core_internal_display_mode_lib * mode_lib,struct dml2_dchub_watermark_regs * out) dml2_core_calcs_get_watermarks() argument
12786 dml2_core_calcs_get_arb_params(const struct dml2_display_cfg * display_cfg,const struct dml2_core_internal_display_mode_lib * mode_lib,struct dml2_display_arb_regs * out) dml2_core_calcs_get_arb_params() argument
12791 dml2_core_calcs_get_pipe_regs(const struct dml2_display_cfg * display_cfg,struct dml2_core_internal_display_mode_lib * mode_lib,struct dml2_dchub_per_pipe_register_set * out,int pipe_index) dml2_core_calcs_get_pipe_regs() argument
12815 dml2_core_calcs_get_global_fams2_programming(const struct dml2_core_internal_display_mode_lib * mode_lib,const struct display_configuation_with_meta * display_cfg,struct dmub_cmd_fams2_global_config * fams2_global_config) dml2_core_calcs_get_global_fams2_programming() argument
12834 dml2_core_calcs_get_stream_fams2_programming(const struct dml2_core_internal_display_mode_lib * mode_lib,const struct display_configuation_with_meta * display_cfg,union dmub_cmd_fams2_config * fams2_base_programming,union dmub_cmd_fams2_config * fams2_sub_programming,enum dml2_pstate_method pstate_method,int plane_index) dml2_core_calcs_get_stream_fams2_programming() argument
12994 dml2_core_calcs_get_plane_support_info(const struct dml2_display_cfg * display_cfg,const struct dml2_core_internal_display_mode_lib * mode_lib,struct core_plane_support_info * out,int plane_idx) dml2_core_calcs_get_plane_support_info() argument
13010 dml2_core_calcs_get_stream_support_info(const struct dml2_display_cfg * display_cfg,const struct dml2_core_internal_display_mode_lib * mode_lib,struct core_stream_support_info * out,int plane_index) dml2_core_calcs_get_stream_support_info() argument
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H A Ddml2_core_utils.c337 … dml2_core_utils_get_stream_output_bpp(double *out_bpp, const struct dml2_display_cfg *display_cfg) in dml2_core_utils_get_stream_output_bpp() argument
339 for (unsigned int k = 0; k < display_cfg->num_planes; k++) { in dml2_core_utils_get_stream_output_bpp()
340 …double bpc = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_inde… in dml2_core_utils_get_stream_output_bpp()
341 …if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.ena… in dml2_core_utils_get_stream_output_bpp()
342 …switch (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.out… in dml2_core_utils_get_stream_output_bpp()
357 …} else if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.… in dml2_core_utils_get_stream_output_bpp()
358 …out_bpp[k] = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_inde… in dml2_core_utils_get_stream_output_bpp()
364 …_VERBOSE("DML::%s: k=%d dsc.enable=%d\n", __func__, k, display_cfg->stream_descriptors[display_cfg in dml2_core_utils_get_stream_output_bpp()
610 void dml2_core_utils_expand_implict_subvp(const struct display_configuation_with_meta *display_cfg,… in dml2_core_utils_expand_implict_subvp() argument
618 memcpy(svp_expanded_display_cfg, &display_cfg->display_config, sizeof(struct dml2_display_cfg)); in dml2_core_utils_expand_implict_subvp()
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H A Ddml2_core_dcn4.c304 static void expand_implict_subvp(const struct display_configuation_with_meta *display_cfg, struct dml2_display_cfg *svp_expanded_display_cfg, in expand_implict_subvp()
312 memcpy(svp_expanded_display_cfg, &display_cfg->display_config, sizeof(struct dml2_display_cfg)); in expand_implict_subvp()
317 if (!display_cfg->display_config.overrides.enable_subvp_implicit_pmo) in expand_implict_subvp()
321 if (!display_cfg->stage3.performed) { in expand_implict_subvp()
326 for (stream_index = 0; stream_index < display_cfg->display_config.num_streams; stream_index++) { in expand_implict_subvp()
327 main_stream = &display_cfg->display_config.stream_descriptors[stream_index]; in expand_implict_subvp()
331 if (display_cfg->stage3.stream_svp_meta[stream_index].valid) { in expand_implict_subvp()
334 main_stream, &display_cfg->stage3.stream_svp_meta[stream_index]); in expand_implict_subvp()
346 for (plane_index = 0; plane_index < display_cfg->display_config.num_planes; plane_index++) { in expand_implict_subvp()
347 main_plane = &display_cfg in expand_implict_subvp()
303 expand_implict_subvp(const struct display_configuation_with_meta * display_cfg,struct dml2_display_cfg * svp_expanded_display_cfg,struct dml2_core_scratch * scratch) expand_implict_subvp() argument
367 pack_mode_programming_params_with_implicit_subvp(struct dml2_core_instance * core,const struct display_configuation_with_meta * display_cfg,const struct dml2_display_cfg * svp_expanded_display_cfg,struct dml2_display_cfg_programming * programming,struct dml2_core_scratch * scratch) pack_mode_programming_params_with_implicit_subvp() argument
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H A Ddml2_core_utils.h18 …dml2_core_utils_get_stream_output_bpp(double *out_bpp, const struct dml2_display_cfg *display_cfg);
32 void dml2_core_utils_expand_implict_subvp(const struct display_configuation_with_meta *display_cfg,…
H A Ddml2_core_shared_types.h357 unsigned int num_active_planes; // <brief As determined by either e2e_pipe_param or display_cfg
1166 unsigned int num_active_planes; // <brief As determined by either e2e_pipe_param or display_cfg
1314 const struct dml2_display_cfg *display_cfg;
1440 const struct dml2_display_cfg *display_cfg;
1668 const struct dml2_display_cfg *display_cfg;
1722 const struct dml2_display_cfg *display_cfg;
1776 const struct dml2_display_cfg *display_cfg;
1867 const struct dml2_display_cfg *display_cfg;
1924 const struct dml2_display_cfg *display_cfg;
2213 const struct dml2_display_cfg *display_cfg;
1313 const struct dml2_display_cfg *display_cfg; global() member
1439 const struct dml2_display_cfg *display_cfg; global() member
1665 const struct dml2_display_cfg *display_cfg; global() member
1719 const struct dml2_display_cfg *display_cfg; global() member
1773 const struct dml2_display_cfg *display_cfg; global() member
1864 const struct dml2_display_cfg *display_cfg; global() member
1921 const struct dml2_display_cfg *display_cfg; global() member
2210 const struct dml2_display_cfg *display_cfg; global() member
2243 const struct dml2_display_cfg *display_cfg; global() member
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/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/
H A Ddml2_dpmm_dcn4.c39 if (in_out->display_cfg->stage3.success) in get_minimum_clocks_for_latency()
40 min_clock_index_for_latency = in_out->display_cfg->stage3.min_clk_index_for_latency; in get_minimum_clocks_for_latency()
42 min_clock_index_for_latency = in_out->display_cfg->stage1.min_clk_index_for_latency; in get_minimum_clocks_for_latency()
64 …const struct dml2_core_mode_support_result *mode_support_result = &in_out->display_cfg->mode_suppo… in calculate_system_active_minimums()
70 if (in_out->display_cfg->display_config.hostvm_enable) in calculate_system_active_minimums()
111 …const struct dml2_core_mode_support_result *mode_support_result = &in_out->display_cfg->mode_suppo… in calculate_svp_prefetch_minimums()
186 …const struct dml2_core_mode_support_result *mode_support_result = &in_out->display_cfg->mode_suppo… in calculate_idle_minimums()
322 static bool map_soc_min_clocks_to_dpm_fine_grained(struct dml2_display_cfg_programming *display_cfg in map_soc_min_clocks_to_dpm_fine_grained() argument
326 …result = round_up_to_next_dpm(&display_cfg->min_clocks.dcn4x.active.dcfclk_khz, &state_table->dcfc… in map_soc_min_clocks_to_dpm_fine_grained()
328 result = round_up_to_next_dpm(&display_cfg->min_clocks.dcn4x.active.fclk_khz, &state_table->fclk); in map_soc_min_clocks_to_dpm_fine_grained()
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/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/
H A Ddml2_pmo_dcn4_fams2.c235 static int count_planes_with_stream_index(const struct dml2_display_cfg *display_cfg, unsigned int stream_index) in count_planes_with_stream_index() argument
240 for (i = 0; i < display_cfg->num_planes; i++) { in count_planes_with_stream_index()
241 if (display_cfg->plane_descriptors[i].stream_index == stream_index) in count_planes_with_stream_index()
1249 static bool all_planes_match_method(const struct display_configuation_with_meta *display_cfg, int plane_mask, enum dml2_pstate_method method) in all_planes_match_method() argument
1255 if (display_cfg->display_config.plane_descriptors[i].overrides.uclk_pstate_change_strategy != dml2_uclk_pstate_change_strategy_auto && in all_planes_match_method()
1256 display_cfg->display_config.plane_descriptors[i].overrides.uclk_pstate_change_strategy != pstate_method_to_uclk_pstate_strategy_override(method)) in all_planes_match_method()
1318 const struct display_configuation_with_meta *display_cfg, in is_timing_group_schedulable() argument
1330 for (base_stream_idx = 0; base_stream_idx < display_cfg->display_config.num_streams; base_stream_idx++) { in is_timing_group_schedulable()
1345 for (i = base_stream_idx + 1; i < display_cfg->display_config.num_streams; i++) { in is_timing_group_schedulable()
1378 const struct display_configuation_with_meta *display_cfg, in is_config_schedulable() argument
1546 stream_matches_drr_policy(struct dml2_pmo_instance * pmo,const struct display_configuation_with_meta * display_cfg,const enum dml2_pstate_method stream_pstate_method,unsigned int stream_index) stream_matches_drr_policy() argument
1597 validate_pstate_support_strategy_cofunctionality(struct dml2_pmo_instance * pmo,const struct display_configuation_with_meta * display_cfg,const struct dml2_pmo_pstate_strategy * pstate_strategy) validate_pstate_support_strategy_cofunctionality() argument
1665 dcn4_get_vactive_pstate_margin(const struct display_configuation_with_meta * display_cfg,int plane_mask) dcn4_get_vactive_pstate_margin() argument
1680 get_vactive_det_fill_latency_delay_us(const struct display_configuation_with_meta * display_cfg,int plane_mask) get_vactive_det_fill_latency_delay_us() argument
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H A Ddml2_pmo_dcn4_fams2.h37 const struct display_configuation_with_meta *display_cfg,
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/
H A Ddml2_top_soc15.c80 l->test_mcache.validate_admissibility_params.display_cfg = &params->display_config->display_config; in dml2_top_optimization_test_function_mcache()
251 l->mode_support_params.display_cfg = &l->next_candidate_display_cfg; in dml2_top_optimization_perform_optimization_phase()
303 l->mode_support_params.display_cfg = &l->cur_candidate_display_cfg; in dml2_top_optimization_perform_optimization_phase_1()
533 for (plane_index = 0; plane_index < params->display_cfg->num_planes; plane_index++) { in dml2_top_mcache_validate_admissability()
534 if (!params->display_cfg->plane_descriptors[plane_index].surface.dcc.enable) in dml2_top_mcache_validate_admissability()
537 plane = &params->display_cfg->plane_descriptors[plane_index]; in dml2_top_mcache_validate_admissability()
538 stream = &params->display_cfg->stream_descriptors[plane->stream_index]; in dml2_top_mcache_validate_admissability()
791 l->mode_support_params.display_cfg = &l->base_display_config_with_meta; in dml2_top_soc15_check_mode_supported()
832 l->dppm_map_mode_params.display_cfg = &l->base_display_config_with_meta; in dml2_top_soc15_build_mode_programming()
864 l->mode_support_params.display_cfg in dml2_top_soc15_build_mode_programming()
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/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddml2_wrapper_fpu.c98 const struct dml_display_cfg_st *display_cfg, in pack_and_call_dml_mode_support_ex() argument
105 s->mode_support_params.in_display_cfg = display_cfg; in pack_and_call_dml_mode_support_ex()
238 static bool are_timings_requiring_odm_doing_blending(const struct dml_display_cfg_st *display_cfg, in are_timings_requiring_odm_doing_blending() argument
244 for (i = 0; i < display_cfg->num_surfaces; i++) in are_timings_requiring_odm_doing_blending()
245 planes_per_timing[display_cfg->plane.BlendingAndTiming[i]]++; in are_timings_requiring_odm_doing_blending()
255 …figuration_meet_sw_policies(struct dml2_context *ctx, const struct dml_display_cfg_st *display_cfg, in does_configuration_meet_sw_policies() argument
261 if (are_timings_requiring_odm_doing_blending(display_cfg, evaluation_info)) in does_configuration_meet_sw_policies()
H A Ddisplay_mode_util.c744 /// @brief Determine the physical pipe to logical plane mapping using the display_cfg in dml_get_num_active_planes()
745 dml_uint_t dml_get_num_active_planes(const struct dml_display_cfg_st *display_cfg) in dml_get_num_active_planes()
750 if (display_cfg->plane.ViewportWidth[k] > 0) in dml_get_num_active_planes()
759 /// @brief Determine the physical pipe to logical plane mapping using the display_cfg in dml_get_num_active_pipes()
760 dml_uint_t dml_get_num_active_pipes(const struct dml_display_cfg_st *display_cfg) in dml_get_num_active_pipes()
764 for (dml_uint_t j = 0; j < dml_get_num_active_planes(display_cfg); j++) { in dml_get_num_active_pipes()
765 num_active_pipes = num_active_pipes + display_cfg->hw.DPPPerSurface[j]; in dml_get_num_active_pipes()
742 dml_get_num_active_planes(const struct dml_display_cfg_st * display_cfg) dml_get_num_active_planes() argument
757 dml_get_num_active_pipes(const struct dml_display_cfg_st * display_cfg) dml_get_num_active_pipes() argument
H A Ddisplay_mode_core.c374 static void PixelClockAdjustmentForProgressiveToInterlaceUnit(struct dml_display_cfg_st *display_cfg, dml_bool_t ptoi_supported);
2706 static void PixelClockAdjustmentForProgressiveToInterlaceUnit(struct dml_display_cfg_st *display_cfg, dml_bool_t ptoi_supported) in PixelClockAdjustmentForProgressiveToInterlaceUnit()
2708 dml_uint_t num_active_planes = dml_get_num_active_planes(display_cfg); in PixelClockAdjustmentForProgressiveToInterlaceUnit()
2712 display_cfg->output.PixelClockBackEnd[k] = display_cfg->timing.PixelClock[k]; in PixelClockAdjustmentForProgressiveToInterlaceUnit()
2713 if (display_cfg->timing.Interlace[k] == 1 && ptoi_supported == true) { in PixelClockAdjustmentForProgressiveToInterlaceUnit()
2714 display_cfg->timing.PixelClock[k] = 2 * display_cfg->timing.PixelClock[k]; in PixelClockAdjustmentForProgressiveToInterlaceUnit()
10182 const struct dml_display_cfg_st *display_cfg) in mode_support_pwr_states()
10184 mode_lib->ms.cache_display_cfg = *display_cfg; in mode_support_pwr_states() argument
2704 PixelClockAdjustmentForProgressiveToInterlaceUnit(struct dml_display_cfg_st * display_cfg,dml_bool_t ptoi_supported) PixelClockAdjustmentForProgressiveToInterlaceUnit() argument
10090 cache_display_cfg(struct display_mode_lib_st * mode_lib,const struct dml_display_cfg_st * display_cfg) cache_display_cfg() argument
10118 dml_mode_support(struct display_mode_lib_st * mode_lib,dml_uint_t state_idx,const struct dml_display_cfg_st * display_cfg) dml_mode_support() argument
10150 dml_mode_programming(struct display_mode_lib_st * mode_lib,dml_uint_t state_idx,const struct dml_display_cfg_st * display_cfg,bool call_standalone) dml_mode_programming() argument
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/linux/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dsi_dpm.c3445 const struct amd_pp_display_configuration *display_cfg = in si_apply_state_adjust_rules() local
3499 for (i = 0; i < display_cfg->num_display; i++) { in si_apply_state_adjust_rules()
3501 if (display_cfg->displays[i].pixel_clock > 297000) in si_apply_state_adjust_rules()
3682 display_cfg->display_clk, in si_apply_state_adjust_rules()