Searched refs:dispclk (Results 1 – 7 of 7) sorted by relevance
39 u32 dispclk);
471 u32 dispclk) in amdgpu_atombios_crtc_set_disp_eng_pll() argument492 args.v5.usPixelClock = cpu_to_le16(dispclk); in amdgpu_atombios_crtc_set_disp_eng_pll()499 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk); in amdgpu_atombios_crtc_set_disp_eng_pll()
119 if (in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.num_clk_values > 1) { in dml21_calculate_rq_and_dlg_params()121 …in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.clk_values_khz[in_ctx->v21.dml_init.soc_bb.clk_table… in dml21_calculate_rq_and_dlg_params()123 …cn.clk.max_supported_dispclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.clk_values_khz[0]… in dml21_calculate_rq_and_dlg_params()
89 .dispclk = {
332 struct bw_fixed dispclk; member
429 result = round_up_to_next_dpm(&display_cfg->min_clocks.dcn4x.dispclk_khz, &state_table->dispclk); in map_min_clocks_to_dpm()654 dispclk_khz = math_min2(dispclk_khz, in_out->min_clk_table->max_clocks_khz.dispclk); in map_mode_to_soc_dpm()
332 DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dispclk: %d", bw_fixed_to_int(data->dispclk)); in print_bw_calcs_data()