Searched refs:dispclk (Results 1 – 13 of 13) sorted by relevance
87 dml_clk_table->dispclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dispclk_levels; in dcn42_convert_dc_clock_table_to_soc_bb_clock_table()89 if (i < dml_clk_table->dispclk.num_clk_values) { in dcn42_convert_dc_clock_table_to_soc_bb_clock_table()90 dml_clk_table->dispclk.clk_values_khz[i] = dc_clk_table->entries[i].dispclk_mhz * 1000; in dcn42_convert_dc_clock_table_to_soc_bb_clock_table()92 dml_clk_table->dispclk.clk_values_khz[i] = 0; in dcn42_convert_dc_clock_table_to_soc_bb_clock_table()97 …dml_clk_table->dispclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dispclk_levels >= 2 … in dcn42_convert_dc_clock_table_to_soc_bb_clock_table()98 dml_clk_table->dispclk.clk_values_khz[0] = 0; in dcn42_convert_dc_clock_table_to_soc_bb_clock_table()99 …dml_clk_table->dispclk.clk_values_khz[1] = dc_clk_table->entries[dc_clk_table->num_entries_per_clk… in dcn42_convert_dc_clock_table_to_soc_bb_clock_table()
119 if (in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.num_clk_values > 1) { in dml21_calculate_rq_and_dlg_params()121 …in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.clk_values_khz[in_ctx->v21.dml_init.soc_bb.clk_table… in dml21_calculate_rq_and_dlg_params()123 …cn.clk.max_supported_dispclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.clk_values_khz[0]… in dml21_calculate_rq_and_dlg_params()
970 …min_clocks->dispclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.clk_values_khz[lowest_dpm_… in dml21_init_min_clocks_for_dc_state()
39 u32 dispclk);
471 u32 dispclk) in amdgpu_atombios_crtc_set_disp_eng_pll() argument492 args.v5.usPixelClock = cpu_to_le16(dispclk); in amdgpu_atombios_crtc_set_disp_eng_pll()499 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk); in amdgpu_atombios_crtc_set_disp_eng_pll()
89 .dispclk = {
433 regs_and_bypass->dispclk = internal.CLK8_CLK0_CURRENT_CNT / 10; in dcn42_dump_clk_registers()456 regs_and_bypass->dispclk, in dcn42_dump_clk_registers()850 clk_mgr->base.boot_snapshot.dispclk; in dcn42_get_max_clock_khz()860 clk_mgr->base.boot_snapshot.dispclk / 3; in dcn42_get_max_clock_khz()
332 struct bw_fixed dispclk; member
429 result = round_up_to_next_dpm(&display_cfg->min_clocks.dcn4x.dispclk_khz, &state_table->dispclk); in map_min_clocks_to_dpm()654 dispclk_khz = math_min2(dispclk_khz, in_out->min_clk_table->max_clocks_khz.dispclk); in map_mode_to_soc_dpm()
1215 v->dispclk = v->dispclk_without_ramping; in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()1218 v->dispclk = v->max_dispclk[number_of_states]; in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()1221 v->dispclk = v->dispclk_with_ramping; in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()1223 v->dppclk = v->dispclk / v->dispclk_dppclk_ratio; in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()1643 …->dstx_after_scaler = 90.0 * v->pixel_clock[k] / v->dppclk + 42.0 * v->pixel_clock[k] / v->dispclk; in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()1654 …total_repeater_delay_time = v->max_inter_dcn_tile_repeaters * (2.0 / v->dppclk + 3.0 / v->dispclk); in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
332 DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dispclk: %d", bw_fixed_to_int(data->dispclk)); in print_bw_calcs_data()
78 clocks->dispclk_khz = dc->clk_mgr->boot_snapshot.dispclk * 1000; in dcn401_initialize_min_clocks()
3519 double dispclk, in CalculateDCFCLKDeepSleepTdlut() argument3569 DCFClkDeepSleepPerSurface[k] = math_max2(DCFClkDeepSleepPerSurface[k], dispclk / 4.0); in CalculateDCFCLKDeepSleepTdlut()7995 mode_lib->ms.max_dispclk_freq_mhz = (double)min_clk_table->max_ss_clocks_khz.dispclk / 1000; in dml_core_mode_support()