Searched refs:dfixed_const (Results 1 – 14 of 14) sorted by relevance
81 tmp.full = dfixed_const(100); in rs690_pm_info()82 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info.ulBootUpMemoryClock)); in rs690_pm_info()85 rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock)); in rs690_pm_info()87 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk); in rs690_pm_info()90 rdev->pm.igp_system_mclk.full = dfixed_const(400); in rs690_pm_info()91 rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock)); in rs690_pm_info()92 rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth); in rs690_pm_info()95 tmp.full = dfixed_const(100); in rs690_pm_info()96 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpSidePortClock)); in rs690_pm_info()99 rdev->pm.igp_system_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpUMAClock)); in rs690_pm_info()[all …]
949 a.full = dfixed_const(100); in rv515_crtc_bandwidth_compute()950 sclk.full = dfixed_const(selected_sclk); in rv515_crtc_bandwidth_compute()953 if (crtc->vsc.full > dfixed_const(2)) in rv515_crtc_bandwidth_compute()954 wm->num_line_pair.full = dfixed_const(2); in rv515_crtc_bandwidth_compute()956 wm->num_line_pair.full = dfixed_const(1); in rv515_crtc_bandwidth_compute()958 b.full = dfixed_const(mode->crtc_hdisplay); in rv515_crtc_bandwidth_compute()959 c.full = dfixed_const(256); in rv515_crtc_bandwidth_compute()963 if (a.full < dfixed_const(4)) { in rv515_crtc_bandwidth_compute()975 a.full = dfixed_const(mode->clock); in rv515_crtc_bandwidth_compute()976 b.full = dfixed_const(1000); in rv515_crtc_bandwidth_compute()[all …]
3284 temp_ff.full = dfixed_const(temp); in r100_bandwidth_update()3291 temp_ff.full = dfixed_const(1000); in r100_bandwidth_update()3292 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */ in r100_bandwidth_update()3294 temp_ff.full = dfixed_const(pixel_bytes1); in r100_bandwidth_update()3298 temp_ff.full = dfixed_const(1000); in r100_bandwidth_update()3299 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */ in r100_bandwidth_update()3301 temp_ff.full = dfixed_const(pixel_bytes2); in r100_bandwidth_update()3347 trcd_ff.full = dfixed_const(mem_trcd); in r100_bandwidth_update()3348 trp_ff.full = dfixed_const(mem_trp); in r100_bandwidth_update()3349 tras_ff.full = dfixed_const(mem_tras); in r100_bandwidth_update()[all …]
1769 a.full = dfixed_const(src_v); in radeon_crtc_scaling_mode_fixup()1770 b.full = dfixed_const(dst_v); in radeon_crtc_scaling_mode_fixup()1772 a.full = dfixed_const(src_h); in radeon_crtc_scaling_mode_fixup()1773 b.full = dfixed_const(dst_h); in radeon_crtc_scaling_mode_fixup()1776 radeon_crtc->vsc.full = dfixed_const(1); in radeon_crtc_scaling_mode_fixup()1777 radeon_crtc->hsc.full = dfixed_const(1); in radeon_crtc_scaling_mode_fixup()
731 a.full = dfixed_const(100); in radeon_update_bandwidth_info()732 rdev->pm.sclk.full = dfixed_const(sclk); in radeon_update_bandwidth_info()734 rdev->pm.mclk.full = dfixed_const(mclk); in radeon_update_bandwidth_info()738 a.full = dfixed_const(16); in radeon_update_bandwidth_info()
37 #define dfixed_const(A) (u32)(((A) << 12))/* + ((B + 0.000122)*4096)) */ macro42 #define dfixed_init(A) { .full = dfixed_const((A)) }51 return dfixed_const(non_frac); in dfixed_floor()58 if (A.full > dfixed_const(non_frac)) in dfixed_ceil()59 return dfixed_const(non_frac + 1); in dfixed_ceil()61 return dfixed_const(non_frac); in dfixed_ceil()
580 a.full = dfixed_const(1000); in dce_v6_0_dram_bandwidth()581 yclk.full = dfixed_const(wm->yclk); in dce_v6_0_dram_bandwidth()583 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v6_0_dram_bandwidth()584 a.full = dfixed_const(10); in dce_v6_0_dram_bandwidth()585 dram_efficiency.full = dfixed_const(7); in dce_v6_0_dram_bandwidth()609 a.full = dfixed_const(1000); in dce_v6_0_dram_bandwidth_for_display()610 yclk.full = dfixed_const(wm->yclk); in dce_v6_0_dram_bandwidth_for_display()612 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v6_0_dram_bandwidth_for_display()613 a.full = dfixed_const(10); in dce_v6_0_dram_bandwidth_for_display()614 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ in dce_v6_0_dram_bandwidth_for_display()[all …]
680 a.full = dfixed_const(1000); in dce_v8_0_dram_bandwidth()681 yclk.full = dfixed_const(wm->yclk); in dce_v8_0_dram_bandwidth()683 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v8_0_dram_bandwidth()684 a.full = dfixed_const(10); in dce_v8_0_dram_bandwidth()685 dram_efficiency.full = dfixed_const(7); in dce_v8_0_dram_bandwidth()709 a.full = dfixed_const(1000); in dce_v8_0_dram_bandwidth_for_display()710 yclk.full = dfixed_const(wm->yclk); in dce_v8_0_dram_bandwidth_for_display()712 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v8_0_dram_bandwidth_for_display()713 a.full = dfixed_const(10); in dce_v8_0_dram_bandwidth_for_display()714 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ in dce_v8_0_dram_bandwidth_for_display()[all …]
727 a.full = dfixed_const(1000); in dce_v10_0_dram_bandwidth()728 yclk.full = dfixed_const(wm->yclk); in dce_v10_0_dram_bandwidth()730 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v10_0_dram_bandwidth()731 a.full = dfixed_const(10); in dce_v10_0_dram_bandwidth()732 dram_efficiency.full = dfixed_const(7); in dce_v10_0_dram_bandwidth()756 a.full = dfixed_const(1000); in dce_v10_0_dram_bandwidth_for_display()757 yclk.full = dfixed_const(wm->yclk); in dce_v10_0_dram_bandwidth_for_display()759 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v10_0_dram_bandwidth_for_display()760 a.full = dfixed_const(10); in dce_v10_0_dram_bandwidth_for_display()761 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ in dce_v10_0_dram_bandwidth_for_display()[all …]
1557 a.full = dfixed_const(src_v); in amdgpu_display_crtc_scaling_mode_fixup()1558 b.full = dfixed_const(dst_v); in amdgpu_display_crtc_scaling_mode_fixup()1560 a.full = dfixed_const(src_h); in amdgpu_display_crtc_scaling_mode_fixup()1561 b.full = dfixed_const(dst_h); in amdgpu_display_crtc_scaling_mode_fixup()1564 amdgpu_crtc->vsc.full = dfixed_const(1); in amdgpu_display_crtc_scaling_mode_fixup()1565 amdgpu_crtc->hsc.full = dfixed_const(1); in amdgpu_display_crtc_scaling_mode_fixup()
153 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1)); in compute_dda_inc()154 inf.full -= dfixed_const(1); in compute_dda_inc()157 dda_inc = min_t(u32, dda_inc, dfixed_const(max)); in compute_dda_inc()
370 pbn.full = dfixed_const(intel_dp_mst_calc_pbn(adjusted_mode->crtc_clock, in intel_dp_mtp_tu_compute_config()
870 return dfixed_const(pbn_div_x100) / 100; in dm_mst_get_pbn_divider()
4471 req_slots = DIV_ROUND_UP(dfixed_const(pbn), topology_state->pbn_div.full); in drm_dp_atomic_find_time_slots()5395 mst_state->pbn_div.full = dfixed_const(0); in drm_dp_mst_atomic_check_payload_alloc_limits()