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Searched refs:ddrphycfg_parents (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/clk/mediatek/
H A Dclk-mt7622.c52 static const char * const ddrphycfg_parents[] = { variable
390 MUX_GATE_FLAGS(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
432 MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", ddrphycfg_parents,
H A Dclk-mt6735-topckgen.c126 static const char * const ddrphycfg_parents[] = { variable
337 …MUX_CLR_SET_UPD(CLK_TOP_DDRPHY_SEL, "ddrphycfg_sel", ddrphycfg_parents, CLK_CFG_0, CLK_CFG_0_SET, …
H A Dclk-mt6795-topckgen.c101 static const char * const ddrphycfg_parents[] = { variable
456 TOP_MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
H A Dclk-mt8173-topckgen.c49 static const char * const ddrphycfg_parents[] = { variable
535 ddrphycfg_parents, 0x0040, 16, 1, 23,
H A Dclk-mt8135.c280 static const char * const ddrphycfg_parents[] = { variable
383 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
H A Dclk-mt8167.c328 static const char * const ddrphycfg_parents[] = { variable
559 MUX(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,