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/linux/Documentation/devicetree/bindings/arm/bcm/
H A Dbrcm,brcmstb.txt169 "brcm,brcmstb-ddr-phy-v71.1"
170 "brcm,brcmstb-ddr-phy-v72.0"
171 "brcm,brcmstb-ddr-phy-v225.1"
172 "brcm,brcmstb-ddr-phy-v240.1"
173 "brcm,brcmstb-ddr-phy-v240.2"
182 - compatible : should contain "brcm,brcmstb-ddr-shimphy-v1.0"
190 See Documentation/devicetree/bindings/memory-controllers/brcm,brcmstb-memc-ddr.yaml for a
203 ddr-phy@f1106000 {
204 compatible = "brcm,brcmstb-ddr-phy-v240.1";
209 compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
[all …]
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dqca,ath79-cpu-intc.txt5 qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties.
20 - qca,ddr-wb-channel-interrupts: List of the interrupts needing a write
22 - qca,ddr-wb-channels: List of phandles to the write buffer channels for
23 each interrupt. If qca,ddr-wb-channel-interrupts is not present the interrupt
34 qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
35 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
43 #qca,ddr-wb-channel-cells = <1>;
/linux/Documentation/devicetree/bindings/mips/brcm/
H A Dsoc.txt75 memc-ddr@2000 {
79 ddr-phy@6000 {
92 "brcm,brcmstb-ddr-phy-v64.5"
93 "brcm,brcmstb-ddr-phy"
99 ddr-phy@6000 {
100 compatible = "brcm,brcmstb-ddr-phy-v64.5";
110 "brcm,bcm7425-memc-ddr"
111 "brcm,bcm7429-memc-ddr"
112 "brcm,bcm7435-memc-ddr" and
113 "brcm,brcmstb-memc-ddr"
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm7445.dtsi239 memc-ddr@2000 {
240 compatible = "brcm,brcmstb-memc-ddr";
244 ddr-phy@6000 {
245 compatible = "brcm,brcmstb-ddr-phy-v240.1";
250 compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
261 memc-ddr@2000 {
262 compatible = "brcm,brcmstb-memc-ddr";
266 ddr-phy@6000 {
267 compatible = "brcm,brcmstb-ddr-phy-v240.1";
272 compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
[all …]
/linux/include/memory/
H A Drenesas-rpc-if.h26 bool ddr; member
32 bool ddr; member
44 bool ddr; member
52 bool ddr; member
/linux/arch/mips/boot/dts/qca/
H A Dar9132.dtsi28 qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
29 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
52 compatible = "qca,ar9132-ddr-controller",
53 "qca,ar7240-ddr-controller";
56 #qca,ddr-wb-channel-cells = <1>;
98 clock-output-names = "cpu", "ddr", "ahb";
H A Dar9331.dtsi28 qca,ddr-wb-channel-interrupts = <2>, <3>;
29 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>;
56 compatible = "qca,ar7240-ddr-controller";
59 #qca,ddr-wb-channel-cells = <1>;
/linux/drivers/media/pci/cx18/
H A Dcx18-cards.c74 .ddr = {
121 .ddr = {
168 .ddr = {
221 .ddr = {
274 .ddr = {
334 .ddr = {
390 .ddr = {
439 .ddr = {
487 .ddr = {
540 .ddr = {
H A Dcx18-firmware.c324 cx18_write_reg(cx, cx->card->ddr.chip_config, CX18_DDR_CHIP_CONFIG); in cx18_init_memory()
328 cx18_write_reg(cx, cx->card->ddr.refresh, CX18_DDR_REFRESH); in cx18_init_memory()
329 cx18_write_reg(cx, cx->card->ddr.timing1, CX18_DDR_TIMING1); in cx18_init_memory()
330 cx18_write_reg(cx, cx->card->ddr.timing2, CX18_DDR_TIMING2); in cx18_init_memory()
335 cx18_write_reg(cx, cx->card->ddr.tune_lane, CX18_DDR_TUNE_LANE); in cx18_init_memory()
336 cx18_write_reg(cx, cx->card->ddr.initial_emrs, CX18_DDR_INITIAL_EMRS); in cx18_init_memory()
/linux/drivers/memory/
H A Drenesas-rpc-if.c191 u32 ddr; /* DRDRENR or SMDRENR */ member
426 rpc->ddr = 0; in rpcif_prepare()
433 if (op->cmd.ddr) in rpcif_prepare()
434 rpc->ddr = RPCIF_SMDRENR_HYPE(0x5); in rpcif_prepare()
450 if (op->addr.ddr) in rpcif_prepare()
451 rpc->ddr |= RPCIF_SMDRENR_ADDRE; in rpcif_prepare()
468 if (op->option.ddr) in rpcif_prepare()
469 rpc->ddr |= RPCIF_SMDRENR_OPDRE; in rpcif_prepare()
488 if (op->data.ddr) in rpcif_prepare()
489 rpc->ddr |= RPCIF_SMDRENR_SPIDRE; in rpcif_prepare()
[all …]
/linux/sound/soc/intel/atom/sst/
H A Dsst_pci.c52 ctx->ddr = pcim_iomap(pci, 0, in sst_platform_get_resources()
54 if (!ctx->ddr) { in sst_platform_get_resources()
58 dev_dbg(ctx->dev, "sst: DDR Ptr %p\n", ctx->ddr); in sst_platform_get_resources()
60 ctx->ddr = NULL; in sst_platform_get_resources()
H A Dsst.c485 fw_save->ddr = kvzalloc(ctx->ddr_end - ctx->ddr_base, GFP_KERNEL); in intel_sst_suspend()
486 if (!fw_save->ddr) { in intel_sst_suspend()
488 goto ddr; in intel_sst_suspend()
494 memcpy32_fromio(fw_save->ddr, ctx->ddr, ctx->ddr_end - ctx->ddr_base); in intel_sst_suspend()
499 ddr: in intel_sst_suspend()
530 memcpy32_toio(ctx->ddr, fw_save->ddr, ctx->ddr_end - ctx->ddr_base); in intel_sst_resume()
535 kvfree(fw_save->ddr); in intel_sst_resume()
/linux/drivers/mtd/hyperbus/
H A Drpc-if.c29 .ddr = true,
33 .ddr = true,
38 .ddr = true,
42 .ddr = true,
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8dxl-ss-ddr.dtsi7 compatible = "fsl,imx8dxl-ddr-pmu", "fsl,imx8-ddr-pmu";
H A Dimx8-ss-ddr.dtsi13 ddr_pmu0: ddr-pmu@5c020000 {
14 compatible = "fsl,imx8-ddr-pmu";
/linux/arch/mips/boot/dts/brcm/
H A Dbcm7435.dtsi560 memc-ddr@2000 {
561 compatible = "brcm,brcmstb-memc-ddr";
565 ddr-phy@6000 {
566 compatible = "brcm,brcmstb-ddr-phy";
571 compatible = "brcm,brcmstb-ddr-shimphy";
587 memc-ddr@2000 {
588 compatible = "brcm,brcmstb-memc-ddr";
592 ddr-phy@6000 {
593 compatible = "brcm,brcmstb-ddr-phy";
598 compatible = "brcm,brcmstb-ddr-shimphy";
H A Dbcm7425.dtsi544 memc-ddr@2000 {
545 compatible = "brcm,brcmstb-memc-ddr";
549 ddr-phy@6000 {
550 compatible = "brcm,brcmstb-ddr-phy";
555 compatible = "brcm,brcmstb-ddr-shimphy";
571 memc-ddr@2000 {
572 compatible = "brcm,brcmstb-memc-ddr";
576 ddr-phy@6000 {
577 compatible = "brcm,brcmstb-ddr-phy";
582 compatible = "brcm,brcmstb-ddr-shimphy";
H A Dbcm7360.dtsi452 memc-ddr@2000 {
453 compatible = "brcm,brcmstb-memc-ddr";
457 ddr-phy@6000 {
458 compatible = "brcm,brcmstb-ddr-phy";
463 compatible = "brcm,brcmstb-ddr-shimphy";
H A Dbcm7362.dtsi448 memc-ddr@2000 {
449 compatible = "brcm,brcmstb-memc-ddr";
453 ddr-phy@6000 {
454 compatible = "brcm,brcmstb-ddr-phy";
459 compatible = "brcm,brcmstb-ddr-shimphy";
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5260-xyref5260.dts97 mmc-ddr-1_8v;
100 samsung,dw-mshc-ddr-timing = <0 2>;
112 samsung,dw-mshc-ddr-timing = <1 2>;
H A Dexynos5410-smdk5410.dts69 mmc-ddr-1_8v;
72 samsung,dw-mshc-ddr-timing = <1 2>;
82 samsung,dw-mshc-ddr-timing = <1 2>;
/linux/Documentation/devicetree/bindings/clock/
H A Dqca,ath79-pll.txt20 - clock-output-names: should be "cpu", "ddr", "ahb"
32 clock-output-names = "cpu", "ddr", "ahb";
/linux/arch/riscv/boot/dts/sophgo/
H A Dcv1812h-huashan-pi.dts50 mmc-ddr-1_8v;
51 mmc-ddr-3_3v;
/linux/arch/arm/boot/dts/st/
H A Dstm32mp157a-icore-stm32mp1.dtsi90 vdd_ddr: regulator-vdd-ddr {
98 vtt_ddr: regulator-vtt-ddr {
107 vref_ddr: regulator-vref-ddr {
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-cardhu-a04.dts19 ddr_reg: regulator-ddr {
21 regulator-name = "ddr";

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