Home
last modified time | relevance | path

Searched refs:ddc (Results 1 – 25 of 152) sorted by relevance

1234567

/linux/drivers/gpu/drm/mediatek/
H A Dmtk_hdmi_ddc.c64 static inline void sif_set_bit(struct mtk_hdmi_ddc *ddc, unsigned int offset, in sif_set_bit() argument
67 writel(readl(ddc->regs + offset) | val, ddc->regs + offset); in sif_set_bit()
70 static inline void sif_clr_bit(struct mtk_hdmi_ddc *ddc, unsigned int offset, in sif_clr_bit() argument
73 writel(readl(ddc->regs + offset) & ~val, ddc->regs + offset); in sif_clr_bit()
76 static inline bool sif_bit_is_set(struct mtk_hdmi_ddc *ddc, unsigned int offset, in sif_bit_is_set() argument
79 return (readl(ddc->regs + offset) & val) == val; in sif_bit_is_set()
82 static inline void sif_write_mask(struct mtk_hdmi_ddc *ddc, unsigned int offset, in sif_write_mask() argument
88 tmp = readl(ddc->regs + offset); in sif_write_mask()
91 writel(tmp, ddc->regs + offset); in sif_write_mask()
94 static inline unsigned int sif_read_mask(struct mtk_hdmi_ddc *ddc, in sif_read_mask() argument
[all …]
H A Dmtk_hdmi_ddc_v2.c44 static int mtk_ddc_check_and_rise_low_bus(struct mtk_hdmi_ddc *ddc) in mtk_ddc_check_and_rise_low_bus() argument
48 regmap_read(ddc->regs, HDCP2X_DDCM_STATUS, &val); in mtk_ddc_check_and_rise_low_bus()
50 regmap_update_bits(ddc->regs, DDC_CTRL, DDC_CTRL_CMD, in mtk_ddc_check_and_rise_low_bus()
58 regmap_read(ddc->regs, DDC_CTRL, &ddc_ctrl); in mtk_ddc_check_and_rise_low_bus()
59 regmap_read(ddc->regs, HPD_DDC_CTRL, &hpd_ddc_ctrl); in mtk_ddc_check_and_rise_low_bus()
60 regmap_read(ddc->regs, HPD_DDC_STATUS, &hpd_ddc_status); in mtk_ddc_check_and_rise_low_bus()
69 static int mtk_ddcm_write_hdmi(struct mtk_hdmi_ddc *ddc, u16 addr_id, in mtk_ddcm_write_hdmi() argument
79 dev_err(ddc->dev, "Invalid DDCM write request\n"); in mtk_ddcm_write_hdmi()
84 mtk_ddc_check_and_rise_low_bus(ddc); in mtk_ddcm_write_hdmi()
86 regmap_update_bits(ddc->regs, HPD_DDC_CTRL, HPD_DDC_DELAY_CNT, in mtk_ddcm_write_hdmi()
[all …]
/linux/drivers/gpu/drm/mgag200/
H A Dmgag200_ddc.c75 struct mgag200_ddc *ddc = data; in mgag200_ddc_algo_bit_data_setsda() local
77 mga_i2c_set(ddc->mdev, ddc->data, state); in mgag200_ddc_algo_bit_data_setsda()
82 struct mgag200_ddc *ddc = data; in mgag200_ddc_algo_bit_data_setscl() local
84 mga_i2c_set(ddc->mdev, ddc->clock, state); in mgag200_ddc_algo_bit_data_setscl()
89 struct mgag200_ddc *ddc = data; in mgag200_ddc_algo_bit_data_getsda() local
91 return (mga_i2c_read_gpio(ddc->mdev) & ddc->data) ? 1 : 0; in mgag200_ddc_algo_bit_data_getsda()
96 struct mgag200_ddc *ddc = data; in mgag200_ddc_algo_bit_data_getscl() local
98 return (mga_i2c_read_gpio(ddc->mdev) & ddc->clock) ? 1 : 0; in mgag200_ddc_algo_bit_data_getscl()
103 struct mgag200_ddc *ddc = i2c_get_adapdata(adapter); in mgag200_ddc_algo_bit_data_pre_xfer() local
104 struct mga_device *mdev = ddc->mdev; in mgag200_ddc_algo_bit_data_pre_xfer()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/
H A Dgpio_service.c488 struct ddc *dal_gpio_create_ddc( in dal_gpio_create_ddc()
496 struct ddc *ddc; in dal_gpio_create_ddc() local
501 ddc = kzalloc_obj(struct ddc); in dal_gpio_create_ddc()
503 if (!ddc) { in dal_gpio_create_ddc()
508 ddc->pin_data = dal_gpio_create( in dal_gpio_create_ddc()
511 if (!ddc->pin_data) { in dal_gpio_create_ddc()
516 ddc->pin_clock = dal_gpio_create( in dal_gpio_create_ddc()
519 if (!ddc->pin_clock) { in dal_gpio_create_ddc()
524 ddc->hw_info = *info; in dal_gpio_create_ddc()
526 ddc->ctx = service->ctx; in dal_gpio_create_ddc()
[all …]
H A Dgpio_base.c69 if (!gpio->hw_container.ddc) { in dal_gpio_open_ex()
238 return gpio->hw_container.ddc; in dal_gpio_get_ddc()
290 gpio->service->factory.funcs->init_ddc_data(&gpio->hw_container.ddc, service->ctx, id, en); in dal_gpio_create()
293 gpio->service->factory.funcs->init_ddc_data(&gpio->hw_container.ddc, service->ctx, id, en); in dal_gpio_create()
324 kfree((*gpio)->hw_container.ddc); in dal_gpio_destroy()
325 (*gpio)->hw_container.ddc = NULL; in dal_gpio_destroy()
329 kfree((*gpio)->hw_container.ddc); in dal_gpio_destroy()
330 (*gpio)->hw_container.ddc = NULL; in dal_gpio_destroy()
/linux/drivers/gpu/drm/ast/
H A Dast_ddc.c42 struct ast_ddc *ddc = data; in ast_ddc_algo_bit_data_setsda() local
43 struct ast_device *ast = ddc->ast; in ast_ddc_algo_bit_data_setsda()
58 struct ast_ddc *ddc = data; in ast_ddc_algo_bit_data_setscl() local
59 struct ast_device *ast = ddc->ast; in ast_ddc_algo_bit_data_setscl()
74 struct ast_ddc *ddc = i2c_get_adapdata(adapter); in ast_ddc_algo_bit_data_pre_xfer() local
75 struct ast_device *ast = ddc->ast; in ast_ddc_algo_bit_data_pre_xfer()
88 struct ast_ddc *ddc = i2c_get_adapdata(adapter); in ast_ddc_algo_bit_data_post_xfer() local
89 struct ast_device *ast = ddc->ast; in ast_ddc_algo_bit_data_post_xfer()
96 struct ast_ddc *ddc = data; in ast_ddc_algo_bit_data_getsda() local
97 struct ast_device *ast = ddc->ast; in ast_ddc_algo_bit_data_getsda()
[all …]
H A Dast_sil164.c84 struct i2c_adapter *ddc; in ast_sil164_output_init() local
92 ddc = ast_ddc_create(ast); in ast_sil164_output_init()
93 if (IS_ERR(ddc)) in ast_sil164_output_init()
94 return PTR_ERR(ddc); in ast_sil164_output_init()
110 DRM_MODE_CONNECTOR_DVII, ddc); in ast_sil164_output_init()
H A Dast_vga.c84 struct i2c_adapter *ddc; in ast_vga_output_init() local
92 ddc = ast_ddc_create(ast); in ast_vga_output_init()
93 if (IS_ERR(ddc)) in ast_vga_output_init()
94 return PTR_ERR(ddc); in ast_vga_output_init()
110 DRM_MODE_CONNECTOR_VGA, ddc); in ast_vga_output_init()
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_i2c_sw.h36 struct ddc *ddc; member
48 struct ddc *ddc,
54 struct ddc *ddc_handle);
H A Ddce_i2c.h35 struct ddc_service *ddc,
41 struct ddc *ddc,
/linux/drivers/gpu/drm/amd/display/dc/gpio/dce110/
H A Dhw_factory_dce110.c116 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); in define_ddc_registers() local
120 ddc->regs = &ddc_data_regs[en]; in define_ddc_registers()
121 ddc->base.regs = &ddc_data_regs[en].gpio; in define_ddc_registers()
124 ddc->regs = &ddc_clk_regs[en]; in define_ddc_registers()
125 ddc->base.regs = &ddc_clk_regs[en].gpio; in define_ddc_registers()
132 ddc->shifts = &ddc_shift; in define_ddc_registers()
133 ddc->masks = &ddc_mask; in define_ddc_registers()
/linux/drivers/gpu/drm/amd/display/dc/gpio/dce80/
H A Dhw_factory_dce80.c120 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); in define_ddc_registers() local
124 ddc->regs = &ddc_data_regs[en]; in define_ddc_registers()
125 ddc->base.regs = &ddc_data_regs[en].gpio; in define_ddc_registers()
128 ddc->regs = &ddc_clk_regs[en]; in define_ddc_registers()
129 ddc->base.regs = &ddc_clk_regs[en].gpio; in define_ddc_registers()
136 ddc->shifts = &ddc_shift; in define_ddc_registers()
137 ddc->masks = &ddc_mask; in define_ddc_registers()
/linux/drivers/gpu/drm/amd/display/dc/gpio/dce60/
H A Dhw_factory_dce60.c120 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); in define_ddc_registers() local
124 ddc->regs = &ddc_data_regs[en]; in define_ddc_registers()
125 ddc->base.regs = &ddc_data_regs[en].gpio; in define_ddc_registers()
128 ddc->regs = &ddc_clk_regs[en]; in define_ddc_registers()
129 ddc->base.regs = &ddc_clk_regs[en].gpio; in define_ddc_registers()
136 ddc->shifts = &ddc_shift; in define_ddc_registers()
137 ddc->masks = &ddc_mask; in define_ddc_registers()
/linux/drivers/gpu/drm/amd/display/dc/gpio/dce120/
H A Dhw_factory_dce120.c133 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); in define_ddc_registers() local
137 ddc->regs = &ddc_data_regs[en]; in define_ddc_registers()
138 ddc->base.regs = &ddc_data_regs[en].gpio; in define_ddc_registers()
141 ddc->regs = &ddc_clk_regs[en]; in define_ddc_registers()
142 ddc->base.regs = &ddc_clk_regs[en].gpio; in define_ddc_registers()
149 ddc->shifts = &ddc_shift; in define_ddc_registers()
150 ddc->masks = &ddc_mask; in define_ddc_registers()
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn10/
H A Dhw_factory_dcn10.c165 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); in define_ddc_registers() local
169 ddc->regs = &ddc_data_regs[en]; in define_ddc_registers()
170 ddc->base.regs = &ddc_data_regs[en].gpio; in define_ddc_registers()
173 ddc->regs = &ddc_clk_regs[en]; in define_ddc_registers()
174 ddc->base.regs = &ddc_clk_regs[en].gpio; in define_ddc_registers()
181 ddc->shifts = &ddc_shift; in define_ddc_registers()
182 ddc->masks = &ddc_mask; in define_ddc_registers()
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn21/
H A Dhw_factory_dcn21.c173 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); in define_ddc_registers() local
177 ddc->regs = &ddc_data_regs_dcn[en]; in define_ddc_registers()
178 ddc->base.regs = &ddc_data_regs_dcn[en].gpio; in define_ddc_registers()
181 ddc->regs = &ddc_clk_regs_dcn[en]; in define_ddc_registers()
182 ddc->base.regs = &ddc_clk_regs_dcn[en].gpio; in define_ddc_registers()
189 ddc->shifts = &ddc_shift[en]; in define_ddc_registers()
190 ddc->masks = &ddc_mask[en]; in define_ddc_registers()
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn32/
H A Dhw_factory_dcn32.c206 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); in define_ddc_registers() local
210 ddc->regs = &ddc_data_regs_dcn[en]; in define_ddc_registers()
211 ddc->base.regs = &ddc_data_regs_dcn[en].gpio; in define_ddc_registers()
214 ddc->regs = &ddc_clk_regs_dcn[en]; in define_ddc_registers()
215 ddc->base.regs = &ddc_clk_regs_dcn[en].gpio; in define_ddc_registers()
222 ddc->shifts = &ddc_shift[en]; in define_ddc_registers()
223 ddc->masks = &ddc_mask[en]; in define_ddc_registers()
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn30/
H A Dhw_factory_dcn30.c202 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); in define_ddc_registers() local
206 ddc->regs = &ddc_data_regs_dcn[en]; in define_ddc_registers()
207 ddc->base.regs = &ddc_data_regs_dcn[en].gpio; in define_ddc_registers()
210 ddc->regs = &ddc_clk_regs_dcn[en]; in define_ddc_registers()
211 ddc->base.regs = &ddc_clk_regs_dcn[en].gpio; in define_ddc_registers()
218 ddc->shifts = &ddc_shift[en]; in define_ddc_registers()
219 ddc->masks = &ddc_mask[en]; in define_ddc_registers()
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn315/
H A Dhw_factory_dcn315.c194 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); in define_ddc_registers() local
198 ddc->regs = &ddc_data_regs_dcn[en]; in define_ddc_registers()
199 ddc->base.regs = &ddc_data_regs_dcn[en].gpio; in define_ddc_registers()
202 ddc->regs = &ddc_clk_regs_dcn[en]; in define_ddc_registers()
203 ddc->base.regs = &ddc_clk_regs_dcn[en].gpio; in define_ddc_registers()
210 ddc->shifts = &ddc_shift[en]; in define_ddc_registers()
211 ddc->masks = &ddc_mask[en]; in define_ddc_registers()
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn20/
H A Dhw_factory_dcn20.c185 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); in define_ddc_registers() local
189 ddc->regs = &ddc_data_regs_dcn[en]; in define_ddc_registers()
190 ddc->base.regs = &ddc_data_regs_dcn[en].gpio; in define_ddc_registers()
193 ddc->regs = &ddc_clk_regs_dcn[en]; in define_ddc_registers()
194 ddc->base.regs = &ddc_clk_regs_dcn[en].gpio; in define_ddc_registers()
201 ddc->shifts = &ddc_shift[en]; in define_ddc_registers()
202 ddc->masks = &ddc_mask[en]; in define_ddc_registers()
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn401/
H A Dhw_factory_dcn401.c198 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); in define_ddc_registers() local
202 ddc->regs = &ddc_data_regs_dcn[en]; in define_ddc_registers()
203 ddc->base.regs = &ddc_data_regs_dcn[en].gpio; in define_ddc_registers()
206 ddc->regs = &ddc_clk_regs_dcn[en]; in define_ddc_registers()
207 ddc->base.regs = &ddc_clk_regs_dcn[en].gpio; in define_ddc_registers()
214 ddc->shifts = &ddc_shift[en]; in define_ddc_registers()
215 ddc->masks = &ddc_mask[en]; in define_ddc_registers()
/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Daux_engine.h92 struct ddc *ddc; member
150 struct ddc_service *ddc,
177 struct ddc *ddc);
/linux/drivers/gpu/drm/amd/display/modules/hdcp/
H A Dhdcp_ddc.c172 success = hdcp->config.ddc.funcs.read_dpcd(hdcp->config.ddc.handle, in read()
188 success = hdcp->config.ddc.funcs.read_i2c( in read()
189 hdcp->config.ddc.handle, in read()
243 success = hdcp->config.ddc.funcs.write_dpcd( in write()
244 hdcp->config.ddc.handle, in write()
262 success = hdcp->config.ddc.funcs.write_i2c( in write()
263 hdcp->config.ddc.handle, in write()
686 return hdcp->config.ddc.funcs.write_dpcd(hdcp->config.ddc.handle, cp_irq_addrs, in mod_hdcp_clear_cp_irq_status()
711 return hdcp->config.ddc.funcs.atomic_write_poll_read_aux( in write_stall_read_lc_fw_aux()
712 hdcp->config.ddc.handle, in write_stall_read_lc_fw_aux()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddm_event_log.h34 #define EVENT_LOG_AUX_REQ(ddc, type, action, address, len, data) argument
35 #define EVENT_LOG_AUX_REP(ddc, type, replyStatus, len, data) argument
/linux/drivers/gpu/drm/loongson/
H A Dlsdc_output.h13 struct i2c_adapter *ddc,
18 struct i2c_adapter *ddc,

1234567