| /linux/drivers/gpu/drm/mediatek/ |
| H A D | mtk_hdmi_ddc.c | 65 static inline void sif_set_bit(struct mtk_hdmi_ddc *ddc, unsigned int offset, in sif_set_bit() argument
68 writel(readl(ddc->regs + offset) | val, ddc->regs + offset); in sif_set_bit()
71 static inline void sif_clr_bit(struct mtk_hdmi_ddc *ddc, unsigned int offset, in sif_clr_bit() argument
74 writel(readl(ddc->regs + offset) & ~val, ddc->regs + offset); in sif_clr_bit()
77 static inline bool sif_bit_is_set(struct mtk_hdmi_ddc *ddc, unsigned int offset, in sif_bit_is_set() argument
80 return (readl(ddc->regs + offset) & val) == val; in sif_bit_is_set()
83 static inline void sif_write_mask(struct mtk_hdmi_ddc *ddc, unsigned int offset, in sif_write_mask() argument
89 tmp = readl(ddc->regs + offset); in sif_write_mask()
92 writel(tmp, ddc->regs + offset); in sif_write_mask()
95 static inline unsigned int sif_read_mask(struct mtk_hdmi_ddc *ddc, in sif_read_mask() argument
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| /linux/drivers/gpu/drm/mgag200/ |
| H A D | mgag200_ddc.c | 76 struct mgag200_ddc *ddc = data; in mgag200_ddc_algo_bit_data_setsda() local
78 mga_i2c_set(ddc->mdev, ddc->data, state); in mgag200_ddc_algo_bit_data_setsda()
83 struct mgag200_ddc *ddc = data; in mgag200_ddc_algo_bit_data_setscl() local
85 mga_i2c_set(ddc->mdev, ddc->clock, state); in mgag200_ddc_algo_bit_data_setscl()
90 struct mgag200_ddc *ddc = data; in mgag200_ddc_algo_bit_data_getsda() local
92 return (mga_i2c_read_gpio(ddc->mdev) & ddc->data) ? 1 : 0; in mgag200_ddc_algo_bit_data_getsda()
97 struct mgag200_ddc *ddc = data; in mgag200_ddc_algo_bit_data_getscl() local
99 return (mga_i2c_read_gpio(ddc->mdev) & ddc->clock) ? 1 : 0; in mgag200_ddc_algo_bit_data_getscl()
104 struct mgag200_ddc *ddc = i2c_get_adapdata(adapter); in mgag200_ddc_algo_bit_data_pre_xfer() local
105 struct mga_device *mdev = ddc->mdev; in mgag200_ddc_algo_bit_data_pre_xfer()
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| H A D | mgag200_vga.c | 33 struct i2c_adapter *ddc; in mgag200_vga_output_init() local
45 ddc = mgag200_ddc_create(mdev); in mgag200_vga_output_init()
46 if (IS_ERR(ddc)) { in mgag200_vga_output_init()
47 ret = PTR_ERR(ddc); in mgag200_vga_output_init()
55 DRM_MODE_CONNECTOR_VGA, ddc); in mgag200_vga_output_init()
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| /linux/drivers/gpu/drm/amd/display/dc/link/protocols/ |
| H A D | link_ddc.c | 168 static void ddc_service_destruct(struct ddc_service *ddc) in ddc_service_destruct() argument
170 if (ddc->ddc_pin) in ddc_service_destruct()
171 dal_gpio_destroy_ddc(&ddc->ddc_pin); in ddc_service_destruct()
174 void link_destroy_ddc_service(struct ddc_service **ddc) in link_destroy_ddc_service() argument
176 if (!ddc || !*ddc) { in link_destroy_ddc_service()
180 ddc_service_destruct(*ddc); in link_destroy_ddc_service()
181 kfree(*ddc); in link_destroy_ddc_service()
182 *ddc = NULL; in link_destroy_ddc_service()
186 struct ddc_service *ddc, in set_ddc_transaction_type() argument
189 ddc->transaction_type = type; in set_ddc_transaction_type()
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| H A D | link_ddc.h | 43 void link_destroy_ddc_service(struct ddc_service **ddc);
46 struct ddc_service *ddc,
49 uint32_t link_get_aux_defer_delay(struct ddc_service *ddc);
51 bool link_is_in_aux_transaction_mode(struct ddc_service *ddc);
53 bool try_to_configure_aux_timeout(struct ddc_service *ddc,
57 struct ddc_service *ddc,
72 bool link_aux_transfer_with_retries_no_mutex(struct ddc_service *ddc,
76 struct ddc_service *ddc,
81 struct ddc_service *ddc,
97 void set_dongle_type(struct ddc_service *ddc,
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| /linux/drivers/gpu/drm/sun4i/ |
| H A D | sun4i_hdmi_ddc_clk.c | 65 struct sun4i_ddc *ddc = hw_to_ddc(hw); in sun4i_ddc_round_rate() local
67 return sun4i_ddc_calc_divider(rate, *prate, ddc->pre_div, in sun4i_ddc_round_rate()
68 ddc->m_offset, NULL, NULL); in sun4i_ddc_round_rate()
74 struct sun4i_ddc *ddc = hw_to_ddc(hw); in sun4i_ddc_recalc_rate() local
78 regmap_field_read(ddc->reg, ®); in sun4i_ddc_recalc_rate()
82 return (((parent_rate / ddc->pre_div) / 10) >> n) / in sun4i_ddc_recalc_rate()
83 (m + ddc->m_offset); in sun4i_ddc_recalc_rate()
89 struct sun4i_ddc *ddc = hw_to_ddc(hw); in sun4i_ddc_set_rate() local
92 sun4i_ddc_calc_divider(rate, parent_rate, ddc->pre_div, in sun4i_ddc_set_rate()
93 ddc->m_offset, &div_m, &div_n); in sun4i_ddc_set_rate()
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| /linux/drivers/gpu/drm/ast/ |
| H A D | ast_ddc.c | 42 struct ast_ddc *ddc = data; in ast_ddc_algo_bit_data_setsda() local
43 struct ast_device *ast = ddc->ast; in ast_ddc_algo_bit_data_setsda()
58 struct ast_ddc *ddc = data; in ast_ddc_algo_bit_data_setscl() local
59 struct ast_device *ast = ddc->ast; in ast_ddc_algo_bit_data_setscl()
74 struct ast_ddc *ddc = i2c_get_adapdata(adapter); in ast_ddc_algo_bit_data_pre_xfer() local
75 struct ast_device *ast = ddc->ast; in ast_ddc_algo_bit_data_pre_xfer()
88 struct ast_ddc *ddc = i2c_get_adapdata(adapter); in ast_ddc_algo_bit_data_post_xfer() local
89 struct ast_device *ast = ddc->ast; in ast_ddc_algo_bit_data_post_xfer()
96 struct ast_ddc *ddc = data; in ast_ddc_algo_bit_data_getsda() local
97 struct ast_device *ast = ddc->ast; in ast_ddc_algo_bit_data_getsda()
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| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_i2c_sw.c | 40 struct ddc *ddc, in read_bit_from_ddc() argument
46 dal_gpio_get_value(ddc->pin_data, &value); in read_bit_from_ddc()
48 dal_gpio_get_value(ddc->pin_clock, &value); in read_bit_from_ddc()
54 struct ddc *ddc, in write_bit_to_ddc() argument
61 dal_gpio_set_value(ddc->pin_data, value); in write_bit_to_ddc()
63 dal_gpio_set_value(ddc->pin_clock, value); in write_bit_to_ddc()
70 dal_ddc_close(dce_i2c_sw->ddc); in release_engine_dce_sw()
71 dce_i2c_sw->ddc = NULL; in release_engine_dce_sw()
76 struct ddc *ddc, in wait_for_scl_high_sw() argument
85 if (read_bit_from_ddc(ddc, SCL)) in wait_for_scl_high_sw()
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| H A D | dce_i2c.c | 30 struct ddc_service *ddc, in dce_i2c_oem_device_present() argument
34 struct dc *dc = ddc->ctx->dc; in dce_i2c_oem_device_present()
56 struct ddc *ddc, in dce_i2c_submit_command() argument
62 if (!ddc) { in dce_i2c_submit_command()
72 dce_i2c_hw = acquire_i2c_hw_engine(pool, ddc); in dce_i2c_submit_command()
75 return dce_i2c_submit_command_hw(pool, ddc, cmd, dce_i2c_hw); in dce_i2c_submit_command()
77 dce_i2c_sw.ctx = ddc->ctx; in dce_i2c_submit_command()
78 if (dce_i2c_engine_acquire_sw(&dce_i2c_sw, ddc)) { in dce_i2c_submit_command()
79 return dce_i2c_submit_command_sw(pool, ddc, cmd, &dce_i2c_sw); in dce_i2c_submit_command()
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| H A D | dce_aux.c | 83 dal_ddc_close(engine->ddc); in release_engine()
85 engine->ddc = NULL; in release_engine()
277 EVENT_LOG_AUX_REQ(engine->ddc->pin_data->en, EVENT_LOG_AUX_ORIGIN_NATIVE, in submit_channel_request()
400 struct ddc *ddc) in acquire() argument
407 result = dal_ddc_open(ddc, GPIO_MODE_HARDWARE, in acquire()
414 engine->ddc = ddc; in acquire()
419 engine->ddc = ddc; in acquire()
434 static uint32_t dce_aux_configure_timeout(struct ddc_service *ddc, in dce_aux_configure_timeout() argument
442 struct ddc *ddc_pin = ddc->ddc_pin; in dce_aux_configure_timeout()
443 struct dce_aux *aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]; in dce_aux_configure_timeout()
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| H A D | dce_i2c_sw.h | 36 struct ddc *ddc; member
48 struct ddc *ddc,
54 struct ddc *ddc_handle);
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| /linux/drivers/gpu/drm/amd/display/include/ |
| H A D | gpio_service_interface.h | 71 struct ddc *dal_gpio_create_ddc(
78 struct ddc **ddc);
103 struct ddc *ddc,
108 struct ddc *ddc,
112 const struct ddc *ddc);
115 struct ddc *ddc,
119 struct ddc *ddc);
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| /linux/drivers/gpu/drm/amd/display/dc/link/hwss/ |
| H A D | link_hwss_dio_fixed_vs_pe_retimer.c | 52 link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc, in dp_dio_fixed_vs_pe_retimer_exit_manual_automation()
54 link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc, in dp_dio_fixed_vs_pe_retimer_exit_manual_automation()
56 link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc, in dp_dio_fixed_vs_pe_retimer_exit_manual_automation()
58 link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc, in dp_dio_fixed_vs_pe_retimer_exit_manual_automation()
60 link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc, in dp_dio_fixed_vs_pe_retimer_exit_manual_automation()
62 link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc, in dp_dio_fixed_vs_pe_retimer_exit_manual_automation()
64 link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc, in dp_dio_fixed_vs_pe_retimer_exit_manual_automation()
66 link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc, in dp_dio_fixed_vs_pe_retimer_exit_manual_automation()
68 link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc, in dp_dio_fixed_vs_pe_retimer_exit_manual_automation()
70 link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc, in dp_dio_fixed_vs_pe_retimer_exit_manual_automation()
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| H A D | link_hwss_hpo_fixed_vs_pe_retimer_dp.c | 62 link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc, in dp_hpo_fixed_vs_pe_retimer_set_tx_ffe()
64 link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc, in dp_hpo_fixed_vs_pe_retimer_set_tx_ffe()
66 link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc, in dp_hpo_fixed_vs_pe_retimer_set_tx_ffe()
68 link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc, in dp_hpo_fixed_vs_pe_retimer_set_tx_ffe()
70 link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc, in dp_hpo_fixed_vs_pe_retimer_set_tx_ffe()
92 link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc, in dp_hpo_fixed_vs_pe_retimer_program_override_test_pattern()
94 link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc, in dp_hpo_fixed_vs_pe_retimer_program_override_test_pattern()
96 link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc, in dp_hpo_fixed_vs_pe_retimer_program_override_test_pattern()
98 link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc, in dp_hpo_fixed_vs_pe_retimer_program_override_test_pattern()
100 link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc, in dp_hpo_fixed_vs_pe_retimer_program_override_test_pattern()
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/ |
| H A D | hw_ddc.c | 39 ddc->shifts->field_name, ddc->masks->field_name
42 ddc->base.base.ctx
44 (ddc->regs->reg)
70 struct hw_ddc *ddc = HW_DDC_FROM_BASE(ptr); in set_config() local
77 hw_gpio = &ddc->base; in set_config()
89 switch (config_data->config.ddc.type) { in set_config()
139 if (config_data->config.ddc.data_en_bit_present || in set_config()
140 config_data->config.ddc.clock_en_bit_present) in set_config()
152 if (ddc->regs->dc_gpio_aux_ctrl_5 != 0) { in set_config()
156 if (ddc->regs->phy_aux_cntl != 0) { in set_config()
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| H A D | gpio_base.c | 69 if (!gpio->hw_container.ddc) { in dal_gpio_open_ex()
238 return gpio->hw_container.ddc; in dal_gpio_get_ddc()
290 gpio->service->factory.funcs->init_ddc_data(&gpio->hw_container.ddc, service->ctx, id, en); in dal_gpio_create()
293 gpio->service->factory.funcs->init_ddc_data(&gpio->hw_container.ddc, service->ctx, id, en); in dal_gpio_create()
324 kfree((*gpio)->hw_container.ddc); in dal_gpio_destroy()
325 (*gpio)->hw_container.ddc = NULL; in dal_gpio_destroy()
329 kfree((*gpio)->hw_container.ddc); in dal_gpio_destroy()
330 (*gpio)->hw_container.ddc = NULL; in dal_gpio_destroy()
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| /linux/drivers/gpu/drm/tegra/ |
| H A D | output.c | 39 else if (output->ddc) in tegra_output_connector_get_modes()
40 drm_edid = drm_edid_read_ddc(connector, output->ddc); in tegra_output_connector_get_modes()
99 struct device_node *ddc, *panel; in tegra_output_probe() local
127 ddc = of_parse_phandle(output->of_node, "nvidia,ddc-i2c-bus", 0); in tegra_output_probe()
128 if (ddc) { in tegra_output_probe()
129 output->ddc = of_get_i2c_adapter_by_node(ddc); in tegra_output_probe()
130 of_node_put(ddc); in tegra_output_probe()
132 if (!output->ddc) { in tegra_output_probe()
188 if (output->ddc) in tegra_output_probe()
189 i2c_put_adapter(output->ddc); in tegra_output_probe()
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| /linux/drivers/gpu/drm/loongson/ |
| H A D | lsdc_output_7a1000.c | 45 if (conn->ddc) { in ls7a1000_dpi_connector_get_modes()
81 struct i2c_adapter *ddc = connector->ddc; in ls7a1000_dpi_connector_detect() local
83 if (ddc) { in ls7a1000_dpi_connector_detect()
84 if (drm_probe_ddc(ddc)) in ls7a1000_dpi_connector_detect()
143 struct i2c_adapter *ddc, in ls7a1000_output_init() argument
160 DRM_MODE_CONNECTOR_DPI, ddc); in ls7a1000_output_init()
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dce110/ |
| H A D | hw_factory_dce110.c | 116 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); in define_ddc_registers() local
120 ddc->regs = &ddc_data_regs[en]; in define_ddc_registers()
121 ddc->base.regs = &ddc_data_regs[en].gpio; in define_ddc_registers()
124 ddc->regs = &ddc_clk_regs[en]; in define_ddc_registers()
125 ddc->base.regs = &ddc_clk_regs[en].gpio; in define_ddc_registers()
132 ddc->shifts = &ddc_shift; in define_ddc_registers()
133 ddc->masks = &ddc_mask; in define_ddc_registers()
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dce80/ |
| H A D | hw_factory_dce80.c | 120 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); in define_ddc_registers() local
124 ddc->regs = &ddc_data_regs[en]; in define_ddc_registers()
125 ddc->base.regs = &ddc_data_regs[en].gpio; in define_ddc_registers()
128 ddc->regs = &ddc_clk_regs[en]; in define_ddc_registers()
129 ddc->base.regs = &ddc_clk_regs[en].gpio; in define_ddc_registers()
136 ddc->shifts = &ddc_shift; in define_ddc_registers()
137 ddc->masks = &ddc_mask; in define_ddc_registers()
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dce60/ |
| H A D | hw_factory_dce60.c | 120 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); in define_ddc_registers() local
124 ddc->regs = &ddc_data_regs[en]; in define_ddc_registers()
125 ddc->base.regs = &ddc_data_regs[en].gpio; in define_ddc_registers()
128 ddc->regs = &ddc_clk_regs[en]; in define_ddc_registers()
129 ddc->base.regs = &ddc_clk_regs[en].gpio; in define_ddc_registers()
136 ddc->shifts = &ddc_shift; in define_ddc_registers()
137 ddc->masks = &ddc_mask; in define_ddc_registers()
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dce120/ |
| H A D | hw_factory_dce120.c | 133 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); in define_ddc_registers() local
137 ddc->regs = &ddc_data_regs[en]; in define_ddc_registers()
138 ddc->base.regs = &ddc_data_regs[en].gpio; in define_ddc_registers()
141 ddc->regs = &ddc_clk_regs[en]; in define_ddc_registers()
142 ddc->base.regs = &ddc_clk_regs[en].gpio; in define_ddc_registers()
149 ddc->shifts = &ddc_shift; in define_ddc_registers()
150 ddc->masks = &ddc_mask; in define_ddc_registers()
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn10/ |
| H A D | hw_factory_dcn10.c | 165 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); in define_ddc_registers() local
169 ddc->regs = &ddc_data_regs[en]; in define_ddc_registers()
170 ddc->base.regs = &ddc_data_regs[en].gpio; in define_ddc_registers()
173 ddc->regs = &ddc_clk_regs[en]; in define_ddc_registers()
174 ddc->base.regs = &ddc_clk_regs[en].gpio; in define_ddc_registers()
181 ddc->shifts = &ddc_shift; in define_ddc_registers()
182 ddc->masks = &ddc_mask; in define_ddc_registers()
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| /linux/drivers/gpu/drm/tests/ |
| H A D | drm_connector_test.c | 25 struct i2c_adapter ddc; member
74 strscpy(priv->ddc.name, "dummy-connector-ddc", sizeof(priv->ddc.name)); in drm_test_connector_init()
75 priv->ddc.owner = THIS_MODULE; in drm_test_connector_init()
76 priv->ddc.algo = &dummy_ddc_algorithm; in drm_test_connector_init()
77 priv->ddc.dev.parent = dev; in drm_test_connector_init()
79 ret = i2c_add_adapter(&priv->ddc); in drm_test_connector_init()
82 ret = kunit_add_action_or_reset(test, i2c_del_adapter_wrapper, &priv->ddc); in drm_test_connector_init()
101 &priv->ddc); in drm_test_drmm_connector_init()
134 &priv->ddc); in drm_test_drmm_connector_init_type_valid()
205 &priv->ddc); in drm_test_drm_connector_dynamic_init()
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn21/ |
| H A D | hw_factory_dcn21.c | 173 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); in define_ddc_registers() local
177 ddc->regs = &ddc_data_regs_dcn[en]; in define_ddc_registers()
178 ddc->base.regs = &ddc_data_regs_dcn[en].gpio; in define_ddc_registers()
181 ddc->regs = &ddc_clk_regs_dcn[en]; in define_ddc_registers()
182 ddc->base.regs = &ddc_clk_regs_dcn[en].gpio; in define_ddc_registers()
189 ddc->shifts = &ddc_shift[en]; in define_ddc_registers()
190 ddc->masks = &ddc_mask[en]; in define_ddc_registers()
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