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Searched refs:dcore_offset (Results 1 – 3 of 3) sorted by relevance

/linux/drivers/accel/habanalabs/common/
H A Dsecurity.c308 u32 dcore_offset, u32 num_instances, u32 instance_offset, in hl_init_pb_with_mask() argument
334 i * dcore_offset + j * instance_offset, in hl_init_pb_with_mask()
359 int hl_init_pb(struct hl_device *hdev, u32 num_dcores, u32 dcore_offset, in hl_init_pb() argument
364 return hl_init_pb_with_mask(hdev, num_dcores, dcore_offset, in hl_init_pb()
388 u32 dcore_offset, u32 num_instances, u32 instance_offset, in hl_init_pb_ranges_with_mask() argument
418 i * dcore_offset + j * instance_offset, in hl_init_pb_ranges_with_mask()
446 u32 dcore_offset, u32 num_instances, u32 instance_offset, in hl_init_pb_ranges() argument
451 return hl_init_pb_ranges_with_mask(hdev, num_dcores, dcore_offset, in hl_init_pb_ranges()
471 int hl_init_pb_single_dcore(struct hl_device *hdev, u32 dcore_offset, in hl_init_pb_single_dcore() argument
494 dcore_offset + i * instance_offset, in hl_init_pb_single_dcore()
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H A Dhabanalabs.h4203 u32 dcore_offset, u32 num_instances, u32 instance_offset,
4206 int hl_init_pb(struct hl_device *hdev, u32 num_dcores, u32 dcore_offset,
4211 u32 dcore_offset, u32 num_instances, u32 instance_offset,
4216 u32 dcore_offset, u32 num_instances, u32 instance_offset,
4220 int hl_init_pb_single_dcore(struct hl_device *hdev, u32 dcore_offset,
4224 int hl_init_pb_ranges_single_dcore(struct hl_device *hdev, u32 dcore_offset,
4229 void hl_ack_pb(struct hl_device *hdev, u32 num_dcores, u32 dcore_offset,
4233 u32 dcore_offset, u32 num_instances, u32 instance_offset,
4235 void hl_ack_pb_single_dcore(struct hl_device *hdev, u32 dcore_offset,
/linux/drivers/accel/habanalabs/gaudi2/
H A Dgaudi2.c7579 u32 dcore_offset = dcore_id * DCORE_OFFSET; in gaudi2_mmu_dcore_prepare() local
7586 WREG32(mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_MMU_BP + dcore_offset, 0); in gaudi2_mmu_dcore_prepare()
7587 WREG32(mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_ASID + dcore_offset, rw_asid); in gaudi2_mmu_dcore_prepare()
7588 WREG32(mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_MMU_BP + dcore_offset, 0); in gaudi2_mmu_dcore_prepare()
7589 WREG32(mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_ASID + dcore_offset, rw_asid); in gaudi2_mmu_dcore_prepare()
7593 WREG32(mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_MMU_BP + dcore_offset, 0); in gaudi2_mmu_dcore_prepare()
7594 WREG32(mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_ASID + dcore_offset, rw_asid); in gaudi2_mmu_dcore_prepare()
7595 WREG32(mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_ASID + dcore_offset, rw_asid); in gaudi2_mmu_dcore_prepare()
7596 WREG32(mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_MMU_BP + dcore_offset, 0); in gaudi2_mmu_dcore_prepare()
7600 WREG32(mmDCORE0_SYNC_MNGR_GLBL_ASID_NONE_SEC_PRIV + dcore_offset, asid); in gaudi2_mmu_dcore_prepare()
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