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Searched refs:dcn3_1_soc (Results 1 – 1 of 1) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.c120 static struct _vcs_dpi_soc_bounding_box_st dcn3_1_soc = { variable
600 memcpy(s, dcn3_1_soc.clock_limits, sizeof(dcn3_1_soc.clock_limits)); in dcn31_update_bw_bounding_box()
605 dcn3_1_soc.num_chans = bw_params->num_channels; in dcn31_update_bw_bounding_box()
619 for (closest_clk_lvl = 0, j = dcn3_1_soc.num_states - 1; j >= 0; j--) { in dcn31_update_bw_bounding_box()
620 if ((unsigned int) dcn3_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { in dcn31_update_bw_bounding_box()
637 dcn3_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz; in dcn31_update_bw_bounding_box()
640 dcn3_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz; in dcn31_update_bw_bounding_box()
643 dcn3_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; in dcn31_update_bw_bounding_box()
644 s[i].dscclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz; in dcn31_update_bw_bounding_box()
645 s[i].dtbclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; in dcn31_update_bw_bounding_box()
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