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Searched refs:dclk (Results 1 – 25 of 51) sorted by relevance

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/linux/drivers/clk/hisilicon/
H A Dclkdivider-hi6220.c49 struct hi6220_clk_divider *dclk = to_hi6220_clk_divider(hw); in hi6220_clkdiv_recalc_rate() local
51 val = readl_relaxed(dclk->reg) >> dclk->shift; in hi6220_clkdiv_recalc_rate()
52 val &= div_mask(dclk->width); in hi6220_clkdiv_recalc_rate()
54 return divider_recalc_rate(hw, parent_rate, val, dclk->table, in hi6220_clkdiv_recalc_rate()
55 CLK_DIVIDER_ROUND_CLOSEST, dclk->width); in hi6220_clkdiv_recalc_rate()
61 struct hi6220_clk_divider *dclk = to_hi6220_clk_divider(hw); in hi6220_clkdiv_determine_rate() local
63 return divider_determine_rate(hw, req, dclk->table, dclk->width, in hi6220_clkdiv_determine_rate()
73 struct hi6220_clk_divider *dclk = to_hi6220_clk_divider(hw); in hi6220_clkdiv_set_rate() local
75 value = divider_get_val(rate, parent_rate, dclk->table, in hi6220_clkdiv_set_rate()
76 dclk->width, CLK_DIVIDER_ROUND_CLOSEST); in hi6220_clkdiv_set_rate()
[all …]
/linux/drivers/clk/eswin/
H A Dclk.c338 struct eswin_divider_clock *dclk = to_div_clk(hw); in clk_div_set_rate() local
343 value = eswin_div_get_val(rate, parent_rate, dclk->width, in clk_div_set_rate()
344 dclk->priv_flag); in clk_div_set_rate()
346 spin_lock_irqsave(dclk->lock, flags); in clk_div_set_rate()
348 val = readl_relaxed(dclk->ctrl_reg); in clk_div_set_rate()
349 val &= ~(clk_div_mask(dclk->width) << dclk->shift); in clk_div_set_rate()
350 val |= (u32)value << dclk->shift; in clk_div_set_rate()
351 writel_relaxed(val, dclk->ctrl_reg); in clk_div_set_rate()
353 spin_unlock_irqrestore(dclk->lock, flags); in clk_div_set_rate()
361 struct eswin_divider_clock *dclk = to_div_clk(hw); in clk_div_recalc_rate() local
[all …]
/linux/drivers/siox/
H A Dsiox-bus-gpio.c19 struct gpio_desc *dclk; member
37 gpiod_set_value_cansleep(ddata->dclk, 0); in siox_gpio_pushpull()
59 gpiod_set_value_cansleep(ddata->dclk, 1); in siox_gpio_pushpull()
61 gpiod_set_value_cansleep(ddata->dclk, 0); in siox_gpio_pushpull()
110 ddata->dclk = devm_gpiod_get(dev, "dclk", GPIOD_OUT_LOW); in siox_gpio_probe()
111 if (IS_ERR(ddata->dclk)) in siox_gpio_probe()
112 return dev_err_probe(dev, PTR_ERR(ddata->dclk), in siox_gpio_probe()
/linux/drivers/clk/
H A Dclk-lmk04832.c261 struct lmk_dclk *dclk; member
1009 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw); in lmk04832_dclk_is_enabled() local
1010 struct lmk04832 *lmk = dclk->lmk; in lmk04832_dclk_is_enabled()
1014 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL3(dclk->id), in lmk04832_dclk_is_enabled()
1024 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw); in lmk04832_dclk_prepare() local
1025 struct lmk04832 *lmk = dclk->lmk; in lmk04832_dclk_prepare()
1028 LMK04832_REG_CLKOUT_CTRL3(dclk->id), in lmk04832_dclk_prepare()
1034 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw); in lmk04832_dclk_unprepare() local
1035 struct lmk04832 *lmk = dclk->lmk; in lmk04832_dclk_unprepare()
1038 LMK04832_REG_CLKOUT_CTRL3(dclk->id), in lmk04832_dclk_unprepare()
[all …]
/linux/drivers/video/fbdev/riva/
H A Dnv_driver.c276 unsigned long dclk = 0; in riva_get_maxdclk() local
286 dclk = 800000; in riva_get_maxdclk()
288 dclk = 1000000; in riva_get_maxdclk()
294 dclk = 1000000; in riva_get_maxdclk()
303 dclk = 800000; in riva_get_maxdclk()
306 dclk = 1000000; in riva_get_maxdclk()
311 return dclk; in riva_get_maxdclk()
/linux/sound/soc/meson/
H A Daxg-pdm.c94 struct clk *dclk; member
188 clk_get_rate(priv->dclk) * 2); in axg_pdm_set_sample_pointer()
253 ret = clk_set_rate(priv->dclk, rate * os); in axg_pdm_hw_params()
276 ret = clk_prepare_enable(priv->dclk); in axg_pdm_startup()
294 clk_disable_unprepare(priv->dclk); in axg_pdm_shutdown()
618 priv->dclk = devm_clk_get(dev, "dclk"); in axg_pdm_probe()
619 if (IS_ERR(priv->dclk)) in axg_pdm_probe()
620 return dev_err_probe(dev, PTR_ERR(priv->dclk), "failed to get dclk\n"); in axg_pdm_probe()
/linux/drivers/video/fbdev/core/
H A Dfbmon.c1022 u32 dclk; member
1110 static u32 fb_get_hblank_by_dclk(u32 dclk, u32 xres) in fb_get_hblank_by_dclk() argument
1114 dclk /= 1000; in fb_get_hblank_by_dclk()
1117 h_period += (M_VAL * xres * 2 * 1000)/(5 * dclk); in fb_get_hblank_by_dclk()
1161 timings->dclk = timings->htotal * timings->hfreq; in fb_timings_vfreq()
1172 timings->dclk = timings->htotal * timings->hfreq; in fb_timings_hfreq()
1177 timings->hblank = fb_get_hblank_by_dclk(timings->dclk, in fb_timings_dclk()
1180 timings->hfreq = timings->dclk/timings->htotal; in fb_timings_dclk()
1272 if (timings->dclk > dclkmax) { in fb_get_mode()
1273 timings->dclk = dclkmax; in fb_get_mode()
[all …]
/linux/drivers/gpu/drm/radeon/
H A Drs780_dpm.c571 (new_ps->dclk == old_ps->dclk)) in rs780_set_uvd_clock_before_set_eng_clock()
577 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_before_set_eng_clock()
588 (new_ps->dclk == old_ps->dclk)) in rs780_set_uvd_clock_after_set_eng_clock()
594 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_after_set_eng_clock()
728 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in rs780_parse_pplib_non_clock_info()
731 rps->dclk = 0; in rs780_parse_pplib_non_clock_info()
735 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rs780_parse_pplib_non_clock_info()
737 rps->dclk = RS780_DEFAULT_DCLK_FREQ; in rs780_parse_pplib_non_clock_info()
944 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_print_power_state()
993 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_debugfs_print_current_performance_level()
H A Dtrinity_dpm.c850 if ((rps->vclk == 0) && (rps->dclk == 0)) in trinity_uvd_clocks_zero()
863 (rps1->dclk == rps2->dclk) && in trinity_uvd_clocks_equal()
895 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks()
906 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks()
1411 (rps->dclk == pi->sys_info.uvd_clock_table_entries[i].dclk)) in trinity_get_uvd_clock_index()
1645 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in trinity_parse_pplib_non_clock_info()
1648 rps->dclk = 0; in trinity_parse_pplib_non_clock_info()
1889 pi->sys_info.uvd_clock_table_entries[i].dclk = in trinity_parse_sys_info_table()
1972 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_print_power_state()
1997 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_debugfs_print_current_performance_level()
H A Dsumo_dpm.c822 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in sumo_setup_uvd_clocks()
839 (new_rps->dclk == old_rps->dclk)) in sumo_set_uvd_clock_before_set_eng_clock()
857 (new_rps->dclk == old_rps->dclk)) in sumo_set_uvd_clock_after_set_eng_clock()
1413 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in sumo_parse_pplib_non_clock_info()
1416 rps->dclk = 0; in sumo_parse_pplib_non_clock_info()
1803 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_print_power_state()
1826 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level()
1834 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level()
H A Dtrinity_dpm.h69 u32 dclk; member
H A Drv770_dpm.c1441 (new_ps->dclk == old_ps->dclk)) in rv770_set_uvd_clock_before_set_eng_clock()
1447 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv770_set_uvd_clock_before_set_eng_clock()
1458 (new_ps->dclk == old_ps->dclk)) in rv770_set_uvd_clock_after_set_eng_clock()
1464 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv770_set_uvd_clock_after_set_eng_clock()
2156 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in rv7xx_parse_pplib_non_clock_info()
2159 rps->dclk = 0; in rv7xx_parse_pplib_non_clock_info()
2163 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rv7xx_parse_pplib_non_clock_info()
2165 rps->dclk = RV770_DEFAULT_DCLK_FREQ; in rv7xx_parse_pplib_non_clock_info()
2441 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv770_dpm_print_power_state()
2485 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv770_dpm_debugfs_print_current_performance_level()
H A Drv6xx_dpm.c1519 (new_ps->dclk == old_ps->dclk)) in rv6xx_set_uvd_clock_before_set_eng_clock()
1525 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv6xx_set_uvd_clock_before_set_eng_clock()
1536 (new_ps->dclk == old_ps->dclk)) in rv6xx_set_uvd_clock_after_set_eng_clock()
1542 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv6xx_set_uvd_clock_after_set_eng_clock()
1804 rps->dclk = RV6XX_DEFAULT_DCLK_FREQ; in rv6xx_parse_pplib_non_clock_info()
1807 rps->dclk = 0; in rv6xx_parse_pplib_non_clock_info()
2014 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv6xx_dpm_print_power_state()
2046 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv6xx_dpm_debugfs_print_current_performance_level()
H A Drv770.c52 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
54 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) in rv770_set_uvd_clocks() argument
61 return evergreen_set_uvd_clocks(rdev, vclk, dclk); in rv770_set_uvd_clocks()
68 if (!vclk || !dclk) { in rv770_set_uvd_clocks()
74 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000, in rv770_set_uvd_clocks()
H A Dkv_dpm.c678 pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk); in kv_populate_uvd_table()
684 (u8)kv_get_clk_bypass(rdev, table->entries[i].dclk); in kv_populate_uvd_table()
693 table->entries[i].dclk, false, &dividers); in kv_populate_uvd_table()
2018 pi->video_start = new_rps->dclk || new_rps->vclk || in kv_apply_state_adjust_rules()
2392 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in kv_parse_pplib_non_clock_info()
2395 rps->dclk = 0; in kv_parse_pplib_non_clock_info()
2651 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in kv_dpm_print_power_state()
/linux/drivers/gpu/drm/renesas/rz-du/
H A Drzg2l_du_crtc.h61 struct clk *dclk; member
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dhwmgr_ppt.h59 uint32_t dclk; /* UVD D-clock */ member
H A Dsmu10_hwmgr.h98 uint32_t dclk; member
H A Dsmu8_hwmgr.h115 uint32_t dclk; member
/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dpower_state.h185 unsigned long dclk; member
/linux/include/linux/mfd/
H A Dsi476x-platform.h121 enum si476x_dclk_config dclk; member
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Ddcn301_smu.h39 uint32_t dclk; member
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu11_driver_if_vangogh.h121 uint32_t dclk; member
/linux/arch/arm/boot/dts/rockchip/
H A Drk3188.dtsi122 reset-names = "axi", "ahb", "dclk";
139 reset-names = "axi", "ahb", "dclk";
365 lcdc1_dclk: lcdc1-dclk {
/linux/drivers/gpu/drm/sun4i/
H A Dsun4i_tcon.h271 struct clk *dclk; member

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