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Searched refs:dclk (Results 1 – 25 of 96) sorted by relevance

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/linux/drivers/gpu/drm/sun4i/
H A Dsun4i_tcon_dclk.c28 struct sun4i_dclk *dclk = hw_to_dclk(hw); in sun4i_dclk_disable() local
30 regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG, in sun4i_dclk_disable()
36 struct sun4i_dclk *dclk = hw_to_dclk(hw); in sun4i_dclk_enable() local
38 return regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG, in sun4i_dclk_enable()
45 struct sun4i_dclk *dclk = hw_to_dclk(hw); in sun4i_dclk_is_enabled() local
48 regmap_read(dclk->regmap, SUN4I_TCON0_DCLK_REG, &val); in sun4i_dclk_is_enabled()
56 struct sun4i_dclk *dclk = hw_to_dclk(hw); in sun4i_dclk_recalc_rate() local
59 regmap_read(dclk->regmap, SUN4I_TCON0_DCLK_REG, &val); in sun4i_dclk_recalc_rate()
73 struct sun4i_dclk *dclk = hw_to_dclk(hw); in sun4i_dclk_round_rate() local
74 struct sun4i_tcon *tcon = dclk->tcon; in sun4i_dclk_round_rate()
[all …]
/linux/drivers/clk/hisilicon/
H A Dclkdivider-hi6220.c49 struct hi6220_clk_divider *dclk = to_hi6220_clk_divider(hw); in hi6220_clkdiv_recalc_rate() local
51 val = readl_relaxed(dclk->reg) >> dclk->shift; in hi6220_clkdiv_recalc_rate()
52 val &= div_mask(dclk->width); in hi6220_clkdiv_recalc_rate()
54 return divider_recalc_rate(hw, parent_rate, val, dclk->table, in hi6220_clkdiv_recalc_rate()
55 CLK_DIVIDER_ROUND_CLOSEST, dclk->width); in hi6220_clkdiv_recalc_rate()
61 struct hi6220_clk_divider *dclk = to_hi6220_clk_divider(hw); in hi6220_clkdiv_round_rate() local
63 return divider_round_rate(hw, rate, prate, dclk->table, in hi6220_clkdiv_round_rate()
64 dclk->width, CLK_DIVIDER_ROUND_CLOSEST); in hi6220_clkdiv_round_rate()
73 struct hi6220_clk_divider *dclk = to_hi6220_clk_divider(hw); in hi6220_clkdiv_set_rate() local
75 value = divider_get_val(rate, parent_rate, dclk->table, in hi6220_clkdiv_set_rate()
[all …]
/linux/drivers/clk/nuvoton/
H A Dclk-ma35d1-divider.c33 struct ma35d1_adc_clk_div *dclk = to_ma35d1_adc_clk_div(hw); in ma35d1_clkdiv_recalc_rate() local
35 val = readl_relaxed(dclk->reg) >> dclk->shift; in ma35d1_clkdiv_recalc_rate()
36 val &= clk_div_mask(dclk->width); in ma35d1_clkdiv_recalc_rate()
38 return divider_recalc_rate(hw, parent_rate, val, dclk->table, in ma35d1_clkdiv_recalc_rate()
39 CLK_DIVIDER_ROUND_CLOSEST, dclk->width); in ma35d1_clkdiv_recalc_rate()
44 struct ma35d1_adc_clk_div *dclk = to_ma35d1_adc_clk_div(hw); in ma35d1_clkdiv_round_rate() local
46 return divider_round_rate(hw, rate, prate, dclk->table, in ma35d1_clkdiv_round_rate()
47 dclk->width, CLK_DIVIDER_ROUND_CLOSEST); in ma35d1_clkdiv_round_rate()
55 struct ma35d1_adc_clk_div *dclk = to_ma35d1_adc_clk_div(hw); in ma35d1_clkdiv_set_rate() local
57 value = divider_get_val(rate, parent_rate, dclk->table, in ma35d1_clkdiv_set_rate()
[all …]
/linux/drivers/siox/
H A Dsiox-bus-gpio.c20 struct gpio_desc *dclk; member
38 gpiod_set_value_cansleep(ddata->dclk, 0); in siox_gpio_pushpull()
60 gpiod_set_value_cansleep(ddata->dclk, 1); in siox_gpio_pushpull()
62 gpiod_set_value_cansleep(ddata->dclk, 0); in siox_gpio_pushpull()
112 ddata->dclk = devm_gpiod_get(dev, "dclk", GPIOD_OUT_LOW); in siox_gpio_probe()
113 if (IS_ERR(ddata->dclk)) in siox_gpio_probe()
114 return dev_err_probe(dev, PTR_ERR(ddata->dclk), in siox_gpio_probe()
/linux/drivers/video/fbdev/riva/
H A Dnv_driver.c276 unsigned long dclk = 0; in riva_get_maxdclk() local
286 dclk = 800000; in riva_get_maxdclk()
288 dclk = 1000000; in riva_get_maxdclk()
294 dclk = 1000000; in riva_get_maxdclk()
303 dclk = 800000; in riva_get_maxdclk()
306 dclk = 1000000; in riva_get_maxdclk()
311 return dclk; in riva_get_maxdclk()
/linux/drivers/gpu/drm/i915/display/
H A Dintel_bw.c22 u16 dclk, t_rp, t_rdpre, t_rc, t_ras, t_rcd; member
55 sp->dclk = DIV_ROUND_UP((16667 * dclk_ratio * dclk_reference) + 500, 1000); in dg1_mchbar_read_qgv_point_info()
59 sp->dclk *= 2; in dg1_mchbar_read_qgv_point_info()
61 if (sp->dclk == 0) in dg1_mchbar_read_qgv_point_info()
82 u16 dclk; in icl_pcode_read_qgv_point_info() local
91 dclk = val & 0xffff; in icl_pcode_read_qgv_point_info()
92 sp->dclk = DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(dev_priv) >= 12 ? 500 : 0), in icl_pcode_read_qgv_point_info()
183 u16 dclk; in mtl_read_qgv_point_info() local
189 dclk = REG_FIELD_GET(MTL_DCLK_MASK, val); in mtl_read_qgv_point_info()
190 sp->dclk = DIV_ROUND_CLOSEST(16667 * dclk, 1000); in mtl_read_qgv_point_info()
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/linux/sound/soc/meson/
H A Daxg-pdm.c94 struct clk *dclk; member
188 clk_get_rate(priv->dclk) * 2); in axg_pdm_set_sample_pointer()
253 ret = clk_set_rate(priv->dclk, rate * os); in axg_pdm_hw_params()
276 ret = clk_prepare_enable(priv->dclk); in axg_pdm_startup()
294 clk_disable_unprepare(priv->dclk); in axg_pdm_shutdown()
618 priv->dclk = devm_clk_get(dev, "dclk"); in axg_pdm_probe()
619 if (IS_ERR(priv->dclk)) in axg_pdm_probe()
620 return dev_err_probe(dev, PTR_ERR(priv->dclk), "failed to get dclk\n"); in axg_pdm_probe()
/linux/drivers/gpu/drm/renesas/rz-du/
H A Drzg2l_du_crtc.c72 clk_prepare_enable(rcrtc->rzg2l_clocks.dclk); in rzg2l_du_crtc_set_display_timing()
73 clk_set_rate(rcrtc->rzg2l_clocks.dclk, mode_clock); in rzg2l_du_crtc_set_display_timing()
210 clk_disable_unprepare(rcrtc->rzg2l_clocks.dclk); in rzg2l_du_crtc_put()
407 rcrtc->rzg2l_clocks.dclk = devm_clk_get(rcdu->dev, "vclk"); in rzg2l_du_crtc_create()
408 if (IS_ERR(rcrtc->rzg2l_clocks.dclk)) { in rzg2l_du_crtc_create()
410 return PTR_ERR(rcrtc->rzg2l_clocks.dclk); in rzg2l_du_crtc_create()
H A Drzg2l_du_crtc.h61 struct clk *dclk; member
/linux/Documentation/devicetree/bindings/siox/
H A Deckelmann,siox-gpio.txt5 - din-gpios, dout-gpios, dclk-gpios, dld-gpios: references gpios for the
17 dclk-gpios = <&gpio6 9 0>;
/linux/drivers/video/fbdev/core/
H A Dfbmon.c1017 u32 dclk; member
1105 static u32 fb_get_hblank_by_dclk(u32 dclk, u32 xres) in fb_get_hblank_by_dclk() argument
1109 dclk /= 1000; in fb_get_hblank_by_dclk()
1112 h_period += (M_VAL * xres * 2 * 1000)/(5 * dclk); in fb_get_hblank_by_dclk()
1156 timings->dclk = timings->htotal * timings->hfreq; in fb_timings_vfreq()
1167 timings->dclk = timings->htotal * timings->hfreq; in fb_timings_hfreq()
1172 timings->hblank = fb_get_hblank_by_dclk(timings->dclk, in fb_timings_dclk()
1175 timings->hfreq = timings->dclk/timings->htotal; in fb_timings_dclk()
1267 if (timings->dclk > dclkmax) { in fb_get_mode()
1268 timings->dclk = dclkmax; in fb_get_mode()
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/linux/drivers/gpu/drm/radeon/
H A Drs780_dpm.c571 (new_ps->dclk == old_ps->dclk)) in rs780_set_uvd_clock_before_set_eng_clock()
577 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_before_set_eng_clock()
588 (new_ps->dclk == old_ps->dclk)) in rs780_set_uvd_clock_after_set_eng_clock()
594 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_after_set_eng_clock()
728 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in rs780_parse_pplib_non_clock_info()
731 rps->dclk = 0; in rs780_parse_pplib_non_clock_info()
735 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rs780_parse_pplib_non_clock_info()
737 rps->dclk = RS780_DEFAULT_DCLK_FREQ; in rs780_parse_pplib_non_clock_info()
945 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_print_power_state()
994 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_debugfs_print_current_performance_level()
H A Dtrinity_dpm.c850 if ((rps->vclk == 0) && (rps->dclk == 0)) in trinity_uvd_clocks_zero()
863 (rps1->dclk == rps2->dclk) && in trinity_uvd_clocks_equal()
895 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks()
906 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks()
1411 (rps->dclk == pi->sys_info.uvd_clock_table_entries[i].dclk)) in trinity_get_uvd_clock_index()
1645 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in trinity_parse_pplib_non_clock_info()
1648 rps->dclk = 0; in trinity_parse_pplib_non_clock_info()
1890 pi->sys_info.uvd_clock_table_entries[i].dclk = in trinity_parse_sys_info_table()
1973 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_print_power_state()
1998 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_debugfs_print_current_performance_level()
H A Dsumo_dpm.c822 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in sumo_setup_uvd_clocks()
839 (new_rps->dclk == old_rps->dclk)) in sumo_set_uvd_clock_before_set_eng_clock()
857 (new_rps->dclk == old_rps->dclk)) in sumo_set_uvd_clock_after_set_eng_clock()
1413 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in sumo_parse_pplib_non_clock_info()
1416 rps->dclk = 0; in sumo_parse_pplib_non_clock_info()
1804 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_print_power_state()
1827 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level()
1835 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level()
H A Drv770_dpm.c1441 (new_ps->dclk == old_ps->dclk)) in rv770_set_uvd_clock_before_set_eng_clock()
1447 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv770_set_uvd_clock_before_set_eng_clock()
1458 (new_ps->dclk == old_ps->dclk)) in rv770_set_uvd_clock_after_set_eng_clock()
1464 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv770_set_uvd_clock_after_set_eng_clock()
2156 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in rv7xx_parse_pplib_non_clock_info()
2159 rps->dclk = 0; in rv7xx_parse_pplib_non_clock_info()
2163 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rv7xx_parse_pplib_non_clock_info()
2165 rps->dclk = RV770_DEFAULT_DCLK_FREQ; in rv7xx_parse_pplib_non_clock_info()
2442 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv770_dpm_print_power_state()
2486 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv770_dpm_debugfs_print_current_performance_level()
H A Drv6xx_dpm.c1519 (new_ps->dclk == old_ps->dclk)) in rv6xx_set_uvd_clock_before_set_eng_clock()
1525 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv6xx_set_uvd_clock_before_set_eng_clock()
1536 (new_ps->dclk == old_ps->dclk)) in rv6xx_set_uvd_clock_after_set_eng_clock()
1542 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv6xx_set_uvd_clock_after_set_eng_clock()
1804 rps->dclk = RV6XX_DEFAULT_DCLK_FREQ; in rv6xx_parse_pplib_non_clock_info()
1807 rps->dclk = 0; in rv6xx_parse_pplib_non_clock_info()
2015 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv6xx_dpm_print_power_state()
2047 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv6xx_dpm_debugfs_print_current_performance_level()
H A Dradeon_uvd.c949 unsigned vclk, unsigned dclk, in radeon_uvd_calc_upll_dividers() argument
964 vco_min = max(max(vco_min, vclk), dclk); in radeon_uvd_calc_upll_dividers()
985 dclk_div = radeon_uvd_calc_upll_post_div(vco_freq, dclk, in radeon_uvd_calc_upll_dividers()
991 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); in radeon_uvd_calc_upll_dividers()
H A Dtrinity_dpm.h69 u32 dclk; member
/linux/sound/soc/intel/skylake/
H A Dskl-ssp-clk.c
/linux/arch/arm/boot/dts/ti/omap/
H A Ddra7xx-clocks.dtsi361 mpu_dclk_div: clock-mpu-dclk-div {
470 iva_dclk: clock-iva-dclk {
532 core_dpll_out_dclk_div: clock-core-dpll-out-dclk-div {
615 video2_dclk_div: clock-video2-dclk-div {
624 video1_dclk_div: clock-video1-dclk-div {
633 hdmi_dclk_div: clock-hdmi-dclk-div {
706 eve_dclk_div: clock-eve-dclk-div {
1064 sys_clk1_dclk_div: clock-sys-clk1-dclk-div@1c8 {
1074 sys_clk2_dclk_div: clock-sys-clk2-dclk-div@1cc {
1084 per_abe_x1_dclk_div: clock-per-abe-x1-dclk-div@1bc {
[all …]
/linux/drivers/gpu/drm/rockchip/
H A Drockchip_drm_vop.c176 /* vop dclk */
177 struct clk *dclk; member
181 /* vop dclk reset */
634 ret = clk_enable(vop->dclk); in vop_enable()
702 clk_disable(vop->dclk); in vop_enable()
775 clk_disable(vop->dclk); in vop_crtc_atomic_disable()
1243 rate = clk_round_rate(vop->dclk, adjusted_mode->clock * 1000); in vop_crtc_mode_fixup()
1245 rate = clk_round_rate(vop->dclk, in vop_crtc_mode_fixup()
1477 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); in vop_crtc_atomic_enable()
2017 vop->dclk in vop_initial()
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/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dhwmgr_ppt.h59 uint32_t dclk; /* UVD D-clock */ member
/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dpower_state.h185 unsigned long dclk; member
/linux/include/linux/mfd/
H A Dsi476x-platform.h121 enum si476x_dclk_config dclk; member
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Ddcn301_smu.h39 uint32_t dclk; member

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