| /linux/drivers/video/fbdev/geode/ |
| H A D | video_cs5530.c | 98 u32 dcfg; in cs5530_configure_display() local
100 dcfg = readl(par->vid_regs + CS5530_DISPLAY_CONFIG); in cs5530_configure_display()
103 dcfg &= ~(CS5530_DCFG_CRT_SYNC_SKW_MASK | CS5530_DCFG_PWR_SEQ_DLY_MASK in cs5530_configure_display()
110 dcfg |= (CS5530_DCFG_CRT_SYNC_SKW_INIT | CS5530_DCFG_PWR_SEQ_DLY_INIT in cs5530_configure_display()
115 dcfg |= CS5530_DCFG_DAC_PWR_EN; in cs5530_configure_display()
116 dcfg |= CS5530_DCFG_HSYNC_EN | CS5530_DCFG_VSYNC_EN; in cs5530_configure_display()
120 dcfg |= CS5530_DCFG_FP_PWR_EN; in cs5530_configure_display()
121 dcfg |= CS5530_DCFG_FP_DATA_EN; in cs5530_configure_display()
126 dcfg |= CS5530_DCFG_CRT_HSYNC_POL; in cs5530_configure_display()
128 dcfg |= CS5530_DCFG_CRT_VSYNC_POL; in cs5530_configure_display()
[all …]
|
| H A D | video_gx.c | 235 u32 dcfg, misc; in gx_configure_display() local
238 dcfg = read_vp(par, VP_DCFG); in gx_configure_display()
241 dcfg &= ~(VP_DCFG_VSYNC_EN | VP_DCFG_HSYNC_EN); in gx_configure_display()
242 write_vp(par, VP_DCFG, dcfg); in gx_configure_display()
245 dcfg &= ~(VP_DCFG_CRT_SYNC_SKW in gx_configure_display()
250 dcfg |= VP_DCFG_CRT_SYNC_SKW_DEFAULT; in gx_configure_display()
253 dcfg |= VP_DCFG_HSYNC_EN | VP_DCFG_VSYNC_EN; in gx_configure_display()
270 dcfg |= VP_DCFG_CRT_HSYNC_POL; in gx_configure_display()
272 dcfg |= VP_DCFG_CRT_VSYNC_POL; in gx_configure_display()
282 dcfg |= VP_DCFG_CRT_EN | VP_DCFG_DAC_BL_EN; in gx_configure_display()
[all …]
|
| H A D | display_gx.c | 60 u32 gcfg, dcfg; in gx_set_mode() local
68 dcfg = read_dc(par, DC_DISPLAY_CFG); in gx_set_mode()
71 dcfg &= ~DC_DISPLAY_CFG_TGEN; in gx_set_mode()
72 write_dc(par, DC_DISPLAY_CFG, dcfg); in gx_set_mode()
91 dcfg = 0; in gx_set_mode()
108 dcfg |= DC_DISPLAY_CFG_GDEN | DC_DISPLAY_CFG_VDEN | in gx_set_mode()
114 dcfg |= DC_DISPLAY_CFG_DISP_MODE_8BPP; in gx_set_mode()
117 dcfg |= DC_DISPLAY_CFG_DISP_MODE_16BPP; in gx_set_mode()
120 dcfg |= DC_DISPLAY_CFG_DISP_MODE_24BPP; in gx_set_mode()
121 dcfg |= DC_DISPLAY_CFG_PALB; in gx_set_mode()
[all …]
|
| H A D | lxfb_ops.c | 348 unsigned int gcfg, dcfg; in lx_set_mode() local
437 dcfg = DC_DISPLAY_CFG_VDEN; /* Enable video data */ in lx_set_mode()
438 dcfg |= DC_DISPLAY_CFG_GDEN; /* Enable graphics */ in lx_set_mode()
439 dcfg |= DC_DISPLAY_CFG_TGEN; /* Turn on the timing generator */ in lx_set_mode()
440 dcfg |= DC_DISPLAY_CFG_TRUP; /* Update timings immediately */ in lx_set_mode()
441 dcfg |= DC_DISPLAY_CFG_PALB; /* Palette bypass in > 8 bpp modes */ in lx_set_mode()
442 dcfg |= DC_DISPLAY_CFG_VISL; in lx_set_mode()
443 dcfg |= DC_DISPLAY_CFG_DCEN; /* Always center the display */ in lx_set_mode()
449 dcfg |= DC_DISPLAY_CFG_DISP_MODE_8BPP; in lx_set_mode()
453 dcfg |= DC_DISPLAY_CFG_DISP_MODE_16BPP; in lx_set_mode()
[all …]
|
| /linux/drivers/mailbox/ |
| H A D | imx-mailbox.c | 97 const struct imx_mu_dcfg *dcfg; member
168 status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]); in imx_mu_tx_waiting_write()
169 can_write = status & IMX_MU_xSR_TEn(priv->dcfg->type, idx % 4); in imx_mu_tx_waiting_write()
178 imx_mu_write(priv, val, priv->dcfg->xTR + (idx % 4) * 4); in imx_mu_tx_waiting_write()
192 status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]); in imx_mu_rx_waiting_read()
193 can_read = status & IMX_MU_xSR_RFn(priv->dcfg->type, idx % 4); in imx_mu_rx_waiting_read()
202 *val = imx_mu_read(priv, priv->dcfg->xRR + (idx % 4) * 4); in imx_mu_rx_waiting_read()
214 val = imx_mu_read(priv, priv->dcfg->xCR[type]); in imx_mu_xcr_rmw()
217 imx_mu_write(priv, val, priv->dcfg->xCR[type]); in imx_mu_xcr_rmw()
233 imx_mu_write(priv, *arg, priv->dcfg->xTR + cp->idx * 4); in imx_mu_generic_tx()
[all …]
|
| /linux/drivers/nvmem/ |
| H A D | snvs_lpgpr.c | 36 const struct snvs_lpgpr_cfg *dcfg; member
57 const struct snvs_lpgpr_cfg *dcfg = priv->dcfg; in snvs_lpgpr_write() local
61 ret = regmap_read(priv->regmap, dcfg->offset_hplr, &lock_reg); in snvs_lpgpr_write()
68 ret = regmap_read(priv->regmap, dcfg->offset_lplr, &lock_reg); in snvs_lpgpr_write()
75 return regmap_bulk_write(priv->regmap, dcfg->offset + offset, val, in snvs_lpgpr_write()
83 const struct snvs_lpgpr_cfg *dcfg = priv->dcfg; in snvs_lpgpr_read() local
85 return regmap_bulk_read(priv->regmap, dcfg->offset + offset, in snvs_lpgpr_read()
97 const struct snvs_lpgpr_cfg *dcfg; in snvs_lpgpr_probe() local
106 dcfg = of_device_get_match_data(dev); in snvs_lpgpr_probe()
107 if (!dcfg) in snvs_lpgpr_probe()
[all …]
|
| /linux/drivers/iio/adc/ |
| H A D | ti-tsc2046.c | 144 const struct tsc2046_adc_dcfg *dcfg; member
746 const struct tsc2046_adc_dcfg *dcfg; in tsc2046_adc_probe() local
759 dcfg = spi_get_device_match_data(spi); in tsc2046_adc_probe()
760 if (!dcfg) in tsc2046_adc_probe()
775 priv->dcfg = dcfg; in tsc2046_adc_probe()
781 indio_dev->channels = dcfg->channels; in tsc2046_adc_probe()
782 indio_dev->num_channels = dcfg->num_channels; in tsc2046_adc_probe()
|
| /linux/drivers/media/pci/pt1/ |
| H A D | pt1.c | 971 struct tc90522_config dcfg; in pt1_init_frontends() local
975 dcfg = pt1_configs[i].demod_cfg; in pt1_init_frontends()
976 dcfg.tuner_i2c = NULL; in pt1_init_frontends()
980 info->addr, &dcfg); in pt1_init_frontends()
991 tcfg.fe = dcfg.fe; in pt1_init_frontends()
993 info->type, dcfg.tuner_i2c, in pt1_init_frontends()
1000 tcfg.fe = dcfg.fe; in pt1_init_frontends()
1002 info->type, dcfg.tuner_i2c, in pt1_init_frontends()
1009 ret = pt1_init_frontend(pt1->adaps[i], dcfg.fe); in pt1_init_frontends()
|
| /linux/drivers/net/ethernet/atheros/ |
| H A D | ag71xx.c | 362 const struct ag71xx_dcfg *dcfg; member
402 return ag->dcfg->type == type; in ag71xx_is()
792 if (ag->dcfg->tx_hang_workaround && in ag71xx_tx_packets()
1520 skb->len & ag->dcfg->desc_pktlen_mask); in ag71xx_hard_start_xmit()
1605 pktlen_mask = ag->dcfg->desc_pktlen_mask; in ag71xx_rx_packets()
1787 const struct ag71xx_dcfg *dcfg; in ag71xx_probe() local
1805 dcfg = of_device_get_match_data(&pdev->dev); in ag71xx_probe()
1806 if (!dcfg) in ag71xx_probe()
1830 ag->dcfg = dcfg; in ag71xx_probe()
1832 memcpy(ag->fifodata, dcfg->fifodata, sizeof(ag->fifodata)); in ag71xx_probe()
[all …]
|
| /linux/arch/arm64/boot/dts/freescale/ |
| H A D | fsl-ls1012a.dtsi | 101 regmap = <&dcfg>;
288 dcfg: dcfg@1ee0000 { label
289 compatible = "fsl,ls1012a-dcfg",
|
| H A D | fsl-ls1043a.dtsi | 151 regmap = <&dcfg>;
399 dcfg: dcfg@1ee0000 { label
400 compatible = "fsl,ls1043a-dcfg", "syscon";
|
| H A D | fsl-ls1046a.dtsi | 119 regmap = <&dcfg>;
426 dcfg: dcfg@1ee0000 { label
427 compatible = "fsl,ls1046a-dcfg", "syscon";
|
| H A D | fsl-ls1088a.dtsi | 231 dcfg: dcfg@1e00000 { label
232 compatible = "fsl,ls1088a-dcfg", "syscon";
|
| H A D | fsl-ls208xa.dtsi | 269 dcfg: dcfg@1e00000 { label
270 compatible = "fsl,ls2080a-dcfg", "syscon";
|
| H A D | fsl-ls1028a.dtsi | 215 dcfg: syscon@1e00000 { label
218 compatible = "fsl,ls1028a-dcfg", "syscon", "simple-mfd";
|
| H A D | fsl-lx2160a.dtsi | 684 dcfg: syscon@1e00000 { label
685 compatible = "fsl,lx2160a-dcfg", "syscon";
|
| /linux/sound/soc/qcom/qdsp6/ |
| H A D | q6afe.c | 1133 struct afe_digital_clk_cfg dcfg = {0,}; in q6afe_port_set_sysclk() local
1138 dcfg.i2s_cfg_minor_version = AFE_API_VERSION_I2S_CONFIG; in q6afe_port_set_sysclk()
1139 dcfg.clk_val = freq; in q6afe_port_set_sysclk()
1140 dcfg.clk_root = clk_root; in q6afe_port_set_sysclk()
1141 ret = q6afe_set_digital_codec_core_clock(port, &dcfg); in q6afe_port_set_sysclk()
|
| /linux/drivers/staging/media/deprecated/atmel/ |
| H A D | atmel-isc.h | 269 u32 dcfg; member
|
| /linux/drivers/media/platform/microchip/ |
| H A D | microchip-isc.h | 287 u32 dcfg; member
|
| H A D | microchip-isc-base.c | 290 u32 pfe_cfg0, dcfg, mask, pipeline; in isc_configure() local
296 dcfg = isc->config.dcfg_imode | isc->dcfg; in isc_configure()
308 regmap_write(regmap, ISC_DCFG + isc->offsets.dma, dcfg); in isc_configure()
|
| H A D | microchip-sama5d2-isc.c | 475 isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; in microchip_isc_probe()
|
| H A D | microchip-sama7g5-isc.c | 464 isc->dcfg = ISC_DCFG_YMBSIZE_BEATS32 | ISC_DCFG_CMBSIZE_BEATS32; in microchip_xisc_probe()
|
| /linux/arch/arm/boot/dts/nxp/ls/ |
| H A D | ls1021a.dtsi | 79 regmap = <&dcfg>;
139 dcfg: dcfg@1ee0000 { label
140 compatible = "fsl,ls1021a-dcfg", "syscon";
|
| /linux/drivers/net/ethernet/cadence/ |
| H A D | macb_main.c | 3940 u32 dcfg; in macb_configure_caps() local
3948 dcfg = gem_readl(bp, DCFG1); in macb_configure_caps()
3949 if (GEM_BFEXT(IRQCOR, dcfg) == 0) in macb_configure_caps()
3951 if (GEM_BFEXT(NO_PCS, dcfg) == 0) in macb_configure_caps()
3953 dcfg = gem_readl(bp, DCFG12); in macb_configure_caps()
3954 if (GEM_BFEXT(HIGH_SPEED, dcfg) == 1) in macb_configure_caps()
3956 dcfg = gem_readl(bp, DCFG2); in macb_configure_caps()
3957 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0) in macb_configure_caps()
|