| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn32/ |
| H A D | dcn32_dccg.c | 30 #define TO_DCN_DCCG(dccg)\ argument
31 container_of(dccg, struct dcn_dccg, base)
43 dccg->ctx->logger
46 struct dccg *dccg) in dccg32_trigger_dio_fifo_resync() argument
48 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg32_trigger_dio_fifo_resync()
59 struct dccg *dccg, in dccg32_get_pixel_rate_div() argument
64 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg32_get_pixel_rate_div()
101 struct dccg *dccg, in dccg32_set_pixel_rate_div() argument
106 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg32_set_pixel_rate_div()
117 dccg32_get_pixel_rate_div(dccg, otg_inst, &cur_k1, &cur_k2); in dccg32_set_pixel_rate_div()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn21/ |
| H A D | dcn21_dccg.c | 31 #define TO_DCN_DCCG(dccg)\ argument
32 container_of(dccg, struct dcn_dccg, base)
44 dccg->ctx->logger
46 static void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg21_update_dpp_dto() argument
48 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg21_update_dpp_dto()
50 if (dccg->ref_dppclk) { in dccg21_update_dpp_dto()
51 int ref_dppclk = dccg->ref_dppclk; in dccg21_update_dpp_dto()
96 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; in dccg21_update_dpp_dto()
109 struct dccg *dccg21_create( in dccg21_create()
116 struct dccg *base; in dccg21_create()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/ |
| H A D | Makefile | 31 AMD_DAL_DCCG_DCN20 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn20/,$(DCCG_DCN20))
39 AMD_DAL_DCCG_DCN201 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn201/,$(DCCG_DCN201))
47 AMD_DAL_DCCG_DCN21 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn21/,$(DCCG_DCN21))
54 AMD_DAL_DCCG_DCN30 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn30/,$(DCCG_DCN30))
61 AMD_DAL_DCCG_DCN301 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn301/,$(DCCG_DCN301))
69 AMD_DAL_DCCG_DCN31 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn31/,$(DCCG_DCN31))
77 AMD_DAL_DCCG_DCN314 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn314/,$(DCCG_DCN314))
85 AMD_DAL_DCCG_DCN32 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn32/,$(DCCG_DCN32))
93 AMD_DAL_DCCG_DCN35 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn35/,$(DCCG_DCN35))
100 AMD_DAL_DCCG_DCN401 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn401/,$(DCCG_DCN401))
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| H A D | dcn20_clk_mgr.c | 109 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; in dcn20_update_clocks_update_dpp_dto()
119 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i]; in dcn20_update_clocks_update_dpp_dto()
122 clk_mgr->dccg->funcs->update_dpp_dto( in dcn20_update_clocks_update_dpp_dto()
123 clk_mgr->dccg, dpp_inst, dppclk_khz); in dcn20_update_clocks_update_dpp_dto()
155 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; in dcn20_update_clocks_update_dentist() local
168 dccg->funcs->set_fifo_errdet_ovr_en( in dcn20_update_clocks_update_dentist()
169 dccg, in dcn20_update_clocks_update_dentist()
172 dccg->funcs->otg_drop_pixel( in dcn20_update_clocks_update_dentist()
173 dccg, in dcn20_update_clocks_update_dentist()
175 dccg->funcs->set_fifo_errdet_ovr_en( in dcn20_update_clocks_update_dentist()
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| H A D | dcn20_clk_mgr.h | 29 void dcn2_update_clocks(struct clk_mgr *dccg,
44 struct dccg *dccg);
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn201/ |
| H A D | dcn201_dccg.c | 31 #define TO_DCN_DCCG(dccg)\ argument
32 container_of(dccg, struct dcn_dccg, base)
45 dccg->ctx->logger
47 static void dccg201_update_dpp_dto(struct dccg *dccg, int dpp_inst, in dccg201_update_dpp_dto() argument
62 struct dccg *dccg201_create( in dccg201_create()
69 struct dccg *base; in dccg201_create()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn30/ |
| H A D | dcn30_dccg.c | 30 #define TO_DCN_DCCG(dccg)\ argument
31 container_of(dccg, struct dcn_dccg, base)
43 dccg->ctx->logger
55 struct dccg *dccg3_create( in dccg3_create()
62 struct dccg *base; in dccg3_create()
80 struct dccg *dccg30_create( in dccg30_create()
87 struct dccg *base; in dccg30_create()
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| H A D | dcn30_dccg.h | 54 struct dccg *dccg3_create(
60 struct dccg *dccg30_create(
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn301/ |
| H A D | dcn301_dccg.c | 30 #define TO_DCN_DCCG(dccg)\ argument
31 container_of(dccg, struct dcn_dccg, base)
43 dccg->ctx->logger
54 struct dccg *dccg301_create( in dccg301_create()
61 struct dccg *base; in dccg301_create()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_clk_mgr.h | 59 struct dccg *dccg);
66 struct dccg *dccg);
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| /linux/drivers/gpu/drm/amd/display/dc/link/hwss/ |
| H A D | link_hwss_hpo_dp.c | 118 if (link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating) in enable_hpo_dp_link_output()
119 link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating( in enable_hpo_dp_link_output()
120 link->dc->res_pool->dccg, in enable_hpo_dp_link_output()
142 if (link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating) in disable_hpo_dp_link_output()
143 link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating( in disable_hpo_dp_link_output()
144 link->dc->res_pool->dccg, in disable_hpo_dp_link_output()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/ |
| H A D | dcn201_clk_mgr.h | 32 struct dccg *dccg);
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| H A D | dcn201_clk_mgr.c | 182 struct dccg *dccg) in dcn201_clk_mgr_construct() argument
192 clk_mgr->dccg = dccg; in dcn201_clk_mgr_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| H A D | dcn20_hwseq.c | 853 if (dc->res_pool->dccg->funcs->set_pixel_rate_div) in dcn20_enable_stream_timing()
854 dc->res_pool->dccg->funcs->set_pixel_rate_div( in dcn20_enable_stream_timing()
855 dc->res_pool->dccg, in dcn20_enable_stream_timing()
896 struct dccg *dccg = dc->res_pool->dccg; in dcn20_enable_stream_timing() local
900 if (dccg->funcs->set_dtbclk_p_src) in dcn20_enable_stream_timing()
901 dccg->funcs->set_dtbclk_p_src(dccg, DTBCLK0, tg->inst); in dcn20_enable_stream_timing()
908 dccg->funcs->set_dtbclk_dto(dccg, &dto_params); in dcn20_enable_stream_timing()
1688 struct dccg *dccg = dc->res_pool->dccg; in dcn20_update_dchubp_dpp() local
1696 dccg->funcs->update_dpp_dto(dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz); in dcn20_update_dchubp_dpp()
2218 struct dccg *dccg = dc->res_pool->dccg; in dcn20_post_unlock_reset_opp() local
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.h | 33 struct dccg *dccg);
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| H A D | dcn316_clk_mgr.h | 45 struct dccg *dccg);
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| H A D | rn_clk_mgr.h | 47 struct dccg *dccg);
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| H A D | rn_clk_mgr.c | 111 clk_mgr->dccg->ref_dppclk = ref_dpp_clk; in rn_update_clocks_update_dpp_dto()
122 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[dpp_inst]; in rn_update_clocks_update_dpp_dto()
125 clk_mgr->dccg->funcs->update_dpp_dto( in rn_update_clocks_update_dpp_dto()
126 clk_mgr->dccg, dpp_inst, dppclk_khz); in rn_update_clocks_update_dpp_dto()
704 struct dccg *dccg) in rn_clk_mgr_construct() argument
719 clk_mgr->dccg = dccg; in rn_clk_mgr_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| H A D | vg_clk_mgr.h | 48 struct dccg *dccg);
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| H A D | dcn31_clk_mgr.h | 52 struct dccg *dccg);
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| H A D | dcn30_clk_mgr.h | 94 struct dccg *dccg);
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/ |
| H A D | dcn401_clk_mgr.h | 111 struct dccg *dccg);
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 156 if (res_pool->dccg->funcs->dccg_init) in dcn401_init_hw()
157 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn401_init_hw()
180 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, in dcn401_init_hw()
778 if (dc->res_pool->dccg->funcs->set_pixel_rate_div) { in dcn401_enable_stream_timing()
779 dc->res_pool->dccg->funcs->set_pixel_rate_div( in dcn401_enable_stream_timing()
780 dc->res_pool->dccg, pipe_ctx->stream_res.tg->inst, in dcn401_enable_stream_timing()
796 if (dc->res_pool->dccg->funcs->set_dtbclk_p_src) { in dcn401_enable_stream_timing()
798 …dc->res_pool->dccg->funcs->set_dtbclk_p_src(dc->res_pool->dccg, DPREFCLK, pipe_ctx->stream_res.tg-… in dcn401_enable_stream_timing()
949 struct dccg *dccg = dc->res_pool->dccg; in dcn401_enable_stream() local
965 dccg->funcs->set_dpstreamclk(dccg, DPREFCLK, tg->inst, dp_hpo_inst); in dcn401_enable_stream()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | clk_mgr.h | 361 struct dccg;
363 …clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg);
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_hw_sequencer.c | 2250 struct dccg *dccg = params->dccg_set_dto_dscclk_params.dccg; in hwss_dccg_set_dto_dscclk() local
2254 if (dccg && dccg->funcs->set_dto_dscclk) in hwss_dccg_set_dto_dscclk()
2255 dccg->funcs->set_dto_dscclk(dccg, inst, num_slices_h); in hwss_dccg_set_dto_dscclk()
2871 struct dccg *dccg = params->dccg_set_ref_dscclk_params.dccg; in hwss_dccg_set_ref_dscclk() local
2879 if (dccg && dccg->funcs->set_ref_dscclk) in hwss_dccg_set_ref_dscclk()
2880 dccg->funcs->set_ref_dscclk(dccg, dsc_inst); in hwss_dccg_set_ref_dscclk()
2941 struct dccg *dccg = params->dccg_update_dpp_dto_params.dccg; in hwss_dccg_update_dpp_dto() local
2945 if (dccg && dccg->funcs->update_dpp_dto) in hwss_dccg_update_dpp_dto()
2946 dccg->funcs->update_dpp_dto(dccg, dpp_inst, dppclk_khz); in hwss_dccg_update_dpp_dto()
3148 struct dccg *dccg, int inst, int num_slices_h) in hwss_add_dccg_set_dto_dscclk() argument
[all …]
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