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Searched refs:dccg (Results 1 – 25 of 75) sorted by relevance

123

/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn35/
H A Ddcn35_dccg.c31 #define TO_DCN_DCCG(dccg)\ argument
32 container_of(dccg, struct dcn_dccg, base)
45 dccg->ctx->logger
138 static void dccg35_set_dsc_clk_rcg(struct dccg *dccg, int inst, bool allow_rcg) in dccg35_set_dsc_clk_rcg() argument
140 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg35_set_dsc_clk_rcg()
142 if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc && allow_rcg) in dccg35_set_dsc_clk_rcg()
169 struct dccg *dccg, in dccg35_set_symclk32_se_rcg() argument
173 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg35_set_symclk32_se_rcg()
175 if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se && enable) in dccg35_set_symclk32_se_rcg()
208 struct dccg *dccg, in dccg35_set_symclk32_le_rcg() argument
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H A Ddcn35_dccg.h244 struct dccg *dccg35_create(
250 void dccg35_init(struct dccg *dccg);
252 void dccg35_trigger_dio_fifo_resync(struct dccg *dccg);
254 void dccg35_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk);
256 void dccg35_enable_global_fgcg_rep(struct dccg *dccg, bool value);
257 void dccg35_root_gate_disable_control(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_…
259 void dccg35_set_dpstreamclk_root_clock_gating(struct dccg *dccg, int dp_hpo_inst, bool enable);
261 void dccg35_set_hdmistreamclk_root_clock_gating(struct dccg *dccg, bool enable);
263 void dccg35_dpp_root_clock_control(struct dccg *dccg, unsigned int dpp_inst, bool clock_on);
265 void dccg35_disable_symclk32_se(struct dccg *dccg, int hpo_se_inst);
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/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Ddccg.h193 struct dccg { struct
214 void (*update_dpp_dto)(struct dccg *dccg, argument
217 void (*get_dccg_ref_freq)(struct dccg *dccg,
220 void (*set_fifo_errdet_ovr_en)(struct dccg *dccg,
222 void (*otg_add_pixel)(struct dccg *dccg,
224 void (*otg_drop_pixel)(struct dccg *dccg,
226 void (*dccg_init)(struct dccg *dccg);
227 void (*refclk_setup)(struct dccg *dccg); /* Deprecated - for backward compatibility only */
228 void (*allow_clock_gating)(struct dccg *dccg, bool allow);
229 void (*enable_memory_low_power)(struct dccg *dccg, bool enable);
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/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn401/
H A Ddcn401_dccg.c41 #define TO_DCN_DCCG(dccg)\ argument
42 container_of(dccg, struct dcn_dccg, base)
54 dccg->ctx->logger
56 static void dcn401_set_dppclk_enable(struct dccg *dccg, in dcn401_set_dppclk_enable() argument
59 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dcn401_set_dppclk_enable()
78 void dccg401_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg401_update_dpp_dto() argument
80 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg401_update_dpp_dto()
82 if (dccg->ref_dppclk && req_dppclk) { in dccg401_update_dpp_dto()
83 int ref_dppclk = dccg->ref_dppclk; in dccg401_update_dpp_dto()
98 dcn401_set_dppclk_enable(dccg, dpp_inst, true); in dccg401_update_dpp_dto()
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/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn20/
H A Ddcn20_dccg.c32 #define TO_DCN_DCCG(dccg)\ argument
33 container_of(dccg, struct dcn_dccg, base)
45 dccg->ctx->logger
47 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg2_update_dpp_dto() argument
49 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg2_update_dpp_dto()
51 if (dccg->ref_dppclk && req_dppclk) { in dccg2_update_dpp_dto()
52 int ref_dppclk = dccg->ref_dppclk; in dccg2_update_dpp_dto()
74 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; in dccg2_update_dpp_dto()
77 void dccg2_get_dccg_ref_freq(struct dccg *dccg, in dccg2_get_dccg_ref_freq() argument
81 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg2_get_dccg_ref_freq()
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H A Ddcn20_dccg.h499 struct dccg base;
505 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk);
507 void dccg2_get_dccg_ref_freq(struct dccg *dccg,
511 void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg,
513 void dccg2_otg_add_pixel(struct dccg *dccg,
515 void dccg2_otg_drop_pixel(struct dccg *dccg,
519 void dccg2_init(struct dccg *dccg);
521 void dccg2_refclk_setup(struct dccg *dccg);
522 void dccg2_allow_clock_gating(struct dccg *dccg, bool allow);
523 void dccg2_enable_memory_low_power(struct dccg *dccg, bool enable);
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/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn31/
H A Ddcn31_dccg.c32 #define TO_DCN_DCCG(dccg)\ argument
33 container_of(dccg, struct dcn_dccg, base)
45 dccg->ctx->logger
47 void dccg31_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg31_update_dpp_dto() argument
49 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg31_update_dpp_dto()
51 if (dccg->dpp_clock_gated[dpp_inst]) { in dccg31_update_dpp_dto()
59 if (dccg->ref_dppclk && req_dppclk) { in dccg31_update_dpp_dto()
60 int ref_dppclk = dccg->ref_dppclk; in dccg31_update_dpp_dto()
81 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; in dccg31_update_dpp_dto()
98 static void dccg31_enable_dpstreamclk(struct dccg *dccg, int otg_inst) in dccg31_enable_dpstreamclk() argument
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/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn314/
H A Ddcn314_dccg.c34 #define TO_DCN_DCCG(dccg)\ argument
35 container_of(dccg, struct dcn_dccg, base)
47 dccg->ctx->logger
50 struct dccg *dccg) in dccg314_trigger_dio_fifo_resync() argument
52 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg314_trigger_dio_fifo_resync()
60 struct dccg *dccg, in dccg314_get_pixel_rate_div() argument
65 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg314_get_pixel_rate_div()
102 struct dccg *dccg, in dccg314_set_pixel_rate_div() argument
107 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg314_set_pixel_rate_div()
118 dccg314_get_pixel_rate_div(dccg, otg_inst, &cur_k1, &cur_k2); in dccg314_set_pixel_rate_div()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn32/
H A Ddcn32_dccg.c31 #define TO_DCN_DCCG(dccg)\ argument
32 container_of(dccg, struct dcn_dccg, base)
44 dccg->ctx->logger
47 struct dccg *dccg) in dccg32_trigger_dio_fifo_resync() argument
49 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg32_trigger_dio_fifo_resync()
60 struct dccg *dccg, in dccg32_get_pixel_rate_div() argument
65 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg32_get_pixel_rate_div()
102 struct dccg *dccg, in dccg32_set_pixel_rate_div() argument
107 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg32_set_pixel_rate_div()
118 dccg32_get_pixel_rate_div(dccg, otg_inst, &cur_k1, &cur_k2); in dccg32_set_pixel_rate_div()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn21/
H A Ddcn21_dccg.c31 #define TO_DCN_DCCG(dccg)\ argument
32 container_of(dccg, struct dcn_dccg, base)
44 dccg->ctx->logger
46 static void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg21_update_dpp_dto() argument
48 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg21_update_dpp_dto()
50 if (dccg->ref_dppclk) { in dccg21_update_dpp_dto()
51 int ref_dppclk = dccg->ref_dppclk; in dccg21_update_dpp_dto()
96 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; in dccg21_update_dpp_dto()
113 struct dccg *dccg21_create( in dccg21_create()
120 struct dccg *base; in dccg21_create()
/linux/drivers/gpu/drm/amd/display/dc/dccg/
H A DMakefile31 AMD_DAL_DCCG_DCN20 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn20/,$(DCCG_DCN20))
39 AMD_DAL_DCCG_DCN201 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn201/,$(DCCG_DCN201))
47 AMD_DAL_DCCG_DCN21 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn21/,$(DCCG_DCN21))
54 AMD_DAL_DCCG_DCN30 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn30/,$(DCCG_DCN30))
61 AMD_DAL_DCCG_DCN301 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn301/,$(DCCG_DCN301))
69 AMD_DAL_DCCG_DCN31 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn31/,$(DCCG_DCN31))
77 AMD_DAL_DCCG_DCN314 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn314/,$(DCCG_DCN314))
85 AMD_DAL_DCCG_DCN32 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn32/,$(DCCG_DCN32))
93 AMD_DAL_DCCG_DCN35 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn35/,$(DCCG_DCN35))
100 AMD_DAL_DCCG_DCN401 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn401/,$(DCCG_DCN401))
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/
H A Dclk_mgr.c147 … clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg) in dc_clk_mgr_create() argument
232 rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
237 rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
259 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
263 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
267 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
271 dcn201_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
274 dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
285 vg_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
298 dcn31_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
H A Ddcn20_clk_mgr.c109 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; in dcn20_update_clocks_update_dpp_dto()
119 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i]; in dcn20_update_clocks_update_dpp_dto()
122 clk_mgr->dccg->funcs->update_dpp_dto( in dcn20_update_clocks_update_dpp_dto()
123 clk_mgr->dccg, dpp_inst, dppclk_khz); in dcn20_update_clocks_update_dpp_dto()
155 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; in dcn20_update_clocks_update_dentist() local
168 dccg->funcs->set_fifo_errdet_ovr_en( in dcn20_update_clocks_update_dentist()
169 dccg, in dcn20_update_clocks_update_dentist()
172 dccg->funcs->otg_drop_pixel( in dcn20_update_clocks_update_dentist()
173 dccg, in dcn20_update_clocks_update_dentist()
175 dccg->funcs->set_fifo_errdet_ovr_en( in dcn20_update_clocks_update_dentist()
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H A Ddcn20_clk_mgr.h29 void dcn2_update_clocks(struct clk_mgr *dccg,
44 struct dccg *dccg);
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn201/
H A Ddcn201_dccg.c32 #define TO_DCN_DCCG(dccg)\ argument
33 container_of(dccg, struct dcn_dccg, base)
46 dccg->ctx->logger
48 static void dccg201_update_dpp_dto(struct dccg *dccg, int dpp_inst, in dccg201_update_dpp_dto() argument
67 struct dccg *dccg201_create( in dccg201_create()
74 struct dccg *base; in dccg201_create()
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn30/
H A Ddcn30_dccg.c30 #define TO_DCN_DCCG(dccg)\ argument
31 container_of(dccg, struct dcn_dccg, base)
43 dccg->ctx->logger
59 struct dccg *dccg3_create( in dccg3_create()
66 struct dccg *base; in dccg3_create()
84 struct dccg *dccg30_create( in dccg30_create()
91 struct dccg *base; in dccg30_create()
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn301/
H A Ddcn301_dccg.c30 #define TO_DCN_DCCG(dccg)\ argument
31 container_of(dccg, struct dcn_dccg, base)
43 dccg->ctx->logger
58 struct dccg *dccg301_create( in dccg301_create()
65 struct dccg *base; in dccg301_create()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr.c270 struct dccg *dccg = clk_mgr->dccg; in dcn32_update_clocks_update_dtb_dto() local
286 dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params); in dcn32_update_clocks_update_dtb_dto()
319 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; in dcn32_update_clocks_update_dpp_dto()
340 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i]; in dcn32_update_clocks_update_dpp_dto()
343 clk_mgr->dccg->funcs->update_dpp_dto( in dcn32_update_clocks_update_dpp_dto()
344 clk_mgr->dccg, dpp_inst, dppclk_khz); in dcn32_update_clocks_update_dpp_dto()
374 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; in dcn32_update_clocks_update_dentist() local
387 dccg->funcs->set_fifo_errdet_ovr_en( in dcn32_update_clocks_update_dentist()
388 dccg, in dcn32_update_clocks_update_dentist()
391 dccg->funcs->otg_drop_pixel( in dcn32_update_clocks_update_dentist()
[all …]
H A Ddcn32_clk_mgr.h33 struct dccg *dccg);
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_clk_mgr.h59 struct dccg *dccg);
66 struct dccg *dccg);
/linux/drivers/gpu/drm/amd/display/dc/link/hwss/
H A Dlink_hwss_hpo_dp.c118 if (link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating) in enable_hpo_dp_link_output()
119 link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating( in enable_hpo_dp_link_output()
120 link->dc->res_pool->dccg, in enable_hpo_dp_link_output()
142 if (link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating) in disable_hpo_dp_link_output()
143 link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating( in disable_hpo_dp_link_output()
144 link->dc->res_pool->dccg, in disable_hpo_dp_link_output()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.c362 if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->dccg_init) in dcn20_dccg_init()
363 dc->res_pool->dccg->funcs->dccg_init(dc->res_pool->dccg); in dcn20_dccg_init()
838 if (dc->res_pool->dccg->funcs->set_pixel_rate_div) in dcn20_enable_stream_timing()
839 dc->res_pool->dccg->funcs->set_pixel_rate_div( in dcn20_enable_stream_timing()
840 dc->res_pool->dccg, in dcn20_enable_stream_timing()
881 struct dccg *dccg = dc->res_pool->dccg; in dcn20_enable_stream_timing() local
885 if (dccg->funcs->set_dtbclk_p_src) in dcn20_enable_stream_timing()
886 dccg->funcs->set_dtbclk_p_src(dccg, DTBCLK0, tg->inst); in dcn20_enable_stream_timing()
893 dccg->funcs->set_dtbclk_dto(dccg, &dto_params); in dcn20_enable_stream_timing()
1673 struct dccg *dccg = dc->res_pool->dccg; in dcn20_update_dchubp_dpp() local
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn31/
H A Ddcn31_hwseq.c130 if (res_pool->dccg->funcs->dccg_init) in dcn31_init_hw()
131 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn31_init_hw()
141 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, in dcn31_init_hw()
250 …if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gati… in dcn31_init_hw()
251 dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true); in dcn31_init_hw()
292 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc && in dcn31_dsc_pg_control()
294 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc( in dcn31_dsc_pg_control()
295 hws->ctx->dc->res_pool->dccg, dsc_inst); in dcn31_dsc_pg_control()
335 if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on) in dcn31_dsc_pg_control()
336 hws->ctx->dc->res_pool->dccg->funcs->disable_dsc( in dcn31_dsc_pg_control()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/
H A Ddcn201_clk_mgr.h32 struct dccg *dccg);
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
H A Ddcn201_hwseq.c234 if (res_pool->dccg->funcs->dccg_init) in dcn201_init_hw()
235 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn201_init_hw()
247 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, in dcn201_init_hw()
370 …if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gati… in dcn201_init_hw()
371 dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true); in dcn201_init_hw()

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