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Searched refs:dccg (Results 1 – 25 of 25) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn20/
H A Ddcn20_dccg.c32 #define TO_DCN_DCCG(dccg)\ argument
33 container_of(dccg, struct dcn_dccg, base)
45 dccg->ctx->logger
47 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg2_update_dpp_dto() argument
49 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg2_update_dpp_dto()
51 if (dccg->ref_dppclk && req_dppclk) { in dccg2_update_dpp_dto()
52 int ref_dppclk = dccg->ref_dppclk; in dccg2_update_dpp_dto()
74 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; in dccg2_update_dpp_dto()
77 void dccg2_get_dccg_ref_freq(struct dccg *dccg, in dccg2_get_dccg_ref_freq() argument
81 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg2_get_dccg_ref_freq()
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/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn21/
H A Ddcn21_dccg.c31 #define TO_DCN_DCCG(dccg)\ argument
32 container_of(dccg, struct dcn_dccg, base)
44 dccg->ctx->logger
46 static void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg21_update_dpp_dto() argument
48 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg21_update_dpp_dto()
50 if (dccg->ref_dppclk) { in dccg21_update_dpp_dto()
51 int ref_dppclk = dccg->ref_dppclk; in dccg21_update_dpp_dto()
96 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; in dccg21_update_dpp_dto()
114 static void dccg21_init(struct dccg *dccg) in dccg21_init() argument
116 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg21_init()
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H A Ddcn21_dccg.h29 struct dccg *dccg21_create(
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn201/
H A Ddcn201_dccg.c32 #define TO_DCN_DCCG(dccg)\ argument
33 container_of(dccg, struct dcn_dccg, base)
46 dccg->ctx->logger
48 static void dccg201_update_dpp_dto(struct dccg *dccg, int dpp_inst, in dccg201_update_dpp_dto() argument
67 struct dccg *dccg201_create( in dccg201_create()
74 struct dccg *base; in dccg201_create()
H A Ddcn201_dccg.h31 struct dccg *dccg201_create(
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn301/
H A Ddcn301_dccg.c30 #define TO_DCN_DCCG(dccg)\ argument
31 container_of(dccg, struct dcn_dccg, base)
43 dccg->ctx->logger
58 struct dccg *dccg301_create( in dccg301_create()
65 struct dccg *base; in dccg301_create()
H A Ddcn301_dccg.h59 struct dccg *dccg301_create(
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_clk_mgr.h59 struct dccg *dccg);
66 struct dccg *dccg);
H A Ddcn35_clk_mgr.c202 struct dccg *dccg = clk_mgr_internal->dccg; in dcn35_disable_otg_wa() local
233 has_active_hpo = dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(old_pipe) && in dcn35_disable_otg_wa()
234 dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(new_pipe); in dcn35_disable_otg_wa()
242 !dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe)) { in dcn35_disable_otg_wa()
260 struct dccg *dccg = clk_mgr->dccg; in dcn35_update_clocks_update_dtb_dto() local
277 dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { in dcn35_update_clocks_update_dtb_dto()
288 dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params); in dcn35_update_clocks_update_dtb_dto()
301 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; in dcn35_update_clocks_update_dpp_dto()
322 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i]; in dcn35_update_clocks_update_dpp_dto()
325 clk_mgr->dccg->funcs->update_dpp_dto( in dcn35_update_clocks_update_dpp_dto()
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/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn42/
H A Ddcn42_dccg.h244 void dccg42_otg_add_pixel(struct dccg *dccg,
247 void dccg42_otg_drop_pixel(struct dccg *dccg,
249 void dccg42_enable_global_fgcg(struct dccg *dccg, bool value);
250 bool dccg42_get_global_fgcg_status(struct dccg *dccg);
253 struct dccg *dccg,
259 struct dccg *dccg,
264 void dccg42_trigger_dio_fifo_resync(struct dccg *dccg);
266 struct dccg *dccg42_create(
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
H A Ddcn20_clk_mgr.h29 void dcn2_update_clocks(struct clk_mgr *dccg,
44 struct dccg *dccg);
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/
H A Ddcn201_clk_mgr.h32 struct dccg *dccg);
H A Ddcn201_clk_mgr.c182 struct dccg *dccg) in dcn201_clk_mgr_construct() argument
192 clk_mgr->dccg = dccg; in dcn201_clk_mgr_construct()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr.h33 struct dccg *dccg);
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_clk_mgr.h45 struct dccg *dccg);
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
H A Drn_clk_mgr.h47 struct dccg *dccg);
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Dvg_clk_mgr.h48 struct dccg *dccg);
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_clk_mgr.h52 struct dccg *dccg);
H A Ddcn31_clk_mgr.c684 struct dccg *dccg) in dcn31_clk_mgr_construct() argument
694 clk_mgr->base.dccg = dccg; in dcn31_clk_mgr_construct()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30_clk_mgr.h94 struct dccg *dccg);
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn314/
H A Ddcn314_dccg.h202 struct dccg *dccg314_create(
209 struct dccg *dccg,
/linux/drivers/gpu/drm/amd/display/dc/
H A DMakefile25 DC_LIBS = basics bios dml clk_mgr dce gpio hwss irq link dsc resource optc dpp hubbub dccg hubp dio…
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_clk_mgr.c801 struct dccg *dccg) in dcn314_clk_mgr_construct() argument
811 clk_mgr->base.dccg = dccg; in dcn314_clk_mgr_construct()
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn32/
H A Ddcn32_dccg.h119 struct dccg *dccg32_create(
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc.c1146 dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg); in dc_construct()
4068 struct dccg *dccg = dc->res_pool->dccg; in add_link_update_dsc_config_sequence() local
4104 if (dccg && dccg->funcs->set_dto_dscclk && in add_link_update_dsc_config_sequence()
4109 hwss_add_dccg_set_dto_dscclk(seq_state, dccg, dsc->inst, in add_link_update_dsc_config_sequence()
4120 hwss_add_dccg_set_dto_dscclk(seq_state, dccg, odm_dsc->inst, in add_link_update_dsc_config_sequence()
7770 state->dccg.dispclk_khz = dc->clk_mgr->clks.dispclk_khz; in dc_capture_register_software_state()
7777 state->dccg.dppclk_khz[i] = dc->clk_mgr->clks.dppclk_khz; in dc_capture_register_software_state()
7778 state->dccg.pixclk_khz[i] = pipe_ctx->stream->timing.pix_clk_100hz / 10; in dc_capture_register_software_state()
7779 state->dccg.dppclk_enable[i] = 1; in dc_capture_register_software_state()
7784 state->dccg.dpstreamclk_enable[i] = 1; in dc_capture_register_software_state()
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