| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | dccg.h | 193 struct dccg { struct
214 void (*update_dpp_dto)(struct dccg *dccg, argument
217 void (*get_dccg_ref_freq)(struct dccg *dccg,
220 void (*set_fifo_errdet_ovr_en)(struct dccg *dccg,
222 void (*otg_add_pixel)(struct dccg *dccg,
224 void (*otg_drop_pixel)(struct dccg *dccg,
226 void (*dccg_init)(struct dccg *dccg);
227 void (*refclk_setup)(struct dccg *dccg); /* Deprecated - for backward compatibility only */
228 void (*allow_clock_gating)(struct dccg *dccg, bool allow);
229 void (*enable_memory_low_power)(struct dccg *dccg, bool enable);
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn20/ |
| H A D | dcn20_dccg.c | 32 #define TO_DCN_DCCG(dccg)\ argument
33 container_of(dccg, struct dcn_dccg, base)
45 dccg->ctx->logger
47 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg2_update_dpp_dto() argument
49 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg2_update_dpp_dto()
51 if (dccg->ref_dppclk && req_dppclk) { in dccg2_update_dpp_dto()
52 int ref_dppclk = dccg->ref_dppclk; in dccg2_update_dpp_dto()
74 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; in dccg2_update_dpp_dto()
77 void dccg2_get_dccg_ref_freq(struct dccg *dccg, in dccg2_get_dccg_ref_freq() argument
81 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg2_get_dccg_ref_freq()
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| H A D | dcn20_dccg.h | 517 struct dccg base;
523 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk);
525 void dccg2_get_dccg_ref_freq(struct dccg *dccg,
529 void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg,
531 void dccg2_otg_add_pixel(struct dccg *dccg,
533 void dccg2_otg_drop_pixel(struct dccg *dccg,
537 void dccg2_init(struct dccg *dccg);
539 void dccg2_refclk_setup(struct dccg *dccg);
540 void dccg2_allow_clock_gating(struct dccg *dccg, bool allow);
541 void dccg2_enable_memory_low_power(struct dccg *dccg, bool enable);
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn314/ |
| H A D | dcn314_dccg.c | 34 #define TO_DCN_DCCG(dccg)\ argument
35 container_of(dccg, struct dcn_dccg, base)
47 dccg->ctx->logger
50 struct dccg *dccg) in dccg314_trigger_dio_fifo_resync() argument
52 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg314_trigger_dio_fifo_resync()
60 struct dccg *dccg, in dccg314_get_pixel_rate_div() argument
65 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg314_get_pixel_rate_div()
102 struct dccg *dccg, in dccg314_set_pixel_rate_div() argument
107 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg314_set_pixel_rate_div()
118 dccg314_get_pixel_rate_div(dccg, otg_inst, &cur_k1, &cur_k2); in dccg314_set_pixel_rate_div()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn31/ |
| H A D | dcn31_dccg.h | 165 struct dccg *dccg31_create(
171 void dccg31_init(struct dccg *dccg);
174 struct dccg *dccg,
179 struct dccg *dccg,
183 struct dccg *dccg,
188 struct dccg *dccg,
192 struct dccg *dccg,
197 struct dccg *dccg,
203 struct dccg *dccg,
207 struct dccg *dccg,
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn21/ |
| H A D | dcn21_dccg.c | 31 #define TO_DCN_DCCG(dccg)\ argument
32 container_of(dccg, struct dcn_dccg, base)
44 dccg->ctx->logger
46 static void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg21_update_dpp_dto() argument
48 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg21_update_dpp_dto()
50 if (dccg->ref_dppclk) { in dccg21_update_dpp_dto()
51 int ref_dppclk = dccg->ref_dppclk; in dccg21_update_dpp_dto()
96 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; in dccg21_update_dpp_dto()
111 static void dccg21_init(struct dccg *dccg) in dccg21_init() argument
113 if (dccg2_is_s0i3_golden_init_wa_done(dccg)) in dccg21_init()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn35/ |
| H A D | dcn35_dccg.h | 244 struct dccg *dccg35_create(
250 void dccg35_init(struct dccg *dccg);
252 void dccg35_trigger_dio_fifo_resync(struct dccg *dccg);
254 void dccg35_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk);
256 void dccg35_enable_global_fgcg_rep(struct dccg *dccg, bool value);
257 void dccg35_root_gate_disable_control(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_…
259 void dccg35_set_dpstreamclk_root_clock_gating(struct dccg *dccg, int dp_hpo_inst, bool enable);
261 void dccg35_set_hdmistreamclk_root_clock_gating(struct dccg *dccg, bool enable);
263 void dccg35_dpp_root_clock_control(struct dccg *dccg, unsigned int dpp_inst, bool clock_on);
265 void dccg35_disable_symclk32_se(struct dccg *dccg, int hpo_se_inst);
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/ |
| H A D | clk_mgr.c | 148 … clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg) in dc_clk_mgr_create() argument
222 rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
227 rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
249 dcn201_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
253 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
257 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
261 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
264 dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
275 vg_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
288 dcn31_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| H A D | dcn20_clk_mgr.c | 109 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; in dcn20_update_clocks_update_dpp_dto()
119 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i]; in dcn20_update_clocks_update_dpp_dto()
122 clk_mgr->dccg->funcs->update_dpp_dto( in dcn20_update_clocks_update_dpp_dto()
123 clk_mgr->dccg, dpp_inst, dppclk_khz); in dcn20_update_clocks_update_dpp_dto()
155 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; in dcn20_update_clocks_update_dentist() local
168 dccg->funcs->set_fifo_errdet_ovr_en( in dcn20_update_clocks_update_dentist()
169 dccg, in dcn20_update_clocks_update_dentist()
172 dccg->funcs->otg_drop_pixel( in dcn20_update_clocks_update_dentist()
173 dccg, in dcn20_update_clocks_update_dentist()
175 dccg->funcs->set_fifo_errdet_ovr_en( in dcn20_update_clocks_update_dentist()
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| H A D | dcn20_clk_mgr.h | 29 void dcn2_update_clocks(struct clk_mgr *dccg,
44 struct dccg *dccg);
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn201/ |
| H A D | dcn201_dccg.c | 32 #define TO_DCN_DCCG(dccg)\ argument
33 container_of(dccg, struct dcn_dccg, base)
46 dccg->ctx->logger
48 static void dccg201_update_dpp_dto(struct dccg *dccg, int dpp_inst, in dccg201_update_dpp_dto() argument
67 struct dccg *dccg201_create( in dccg201_create()
74 struct dccg *base; in dccg201_create()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn30/ |
| H A D | dcn30_dccg.c | 30 #define TO_DCN_DCCG(dccg)\ argument
31 container_of(dccg, struct dcn_dccg, base)
43 dccg->ctx->logger
59 struct dccg *dccg3_create( in dccg3_create()
66 struct dccg *base; in dccg3_create()
84 struct dccg *dccg30_create( in dccg30_create()
91 struct dccg *base; in dccg30_create()
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| H A D | dcn30_dccg.h | 54 struct dccg *dccg3_create(
60 struct dccg *dccg30_create(
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn301/ |
| H A D | dcn301_dccg.c | 30 #define TO_DCN_DCCG(dccg)\ argument
31 container_of(dccg, struct dcn_dccg, base)
43 dccg->ctx->logger
58 struct dccg *dccg301_create( in dccg301_create()
65 struct dccg *base; in dccg301_create()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_clk_mgr.h | 59 struct dccg *dccg);
66 struct dccg *dccg);
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/ |
| H A D | dcn201_clk_mgr.h | 32 struct dccg *dccg);
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| H A D | dcn201_clk_mgr.c | 182 struct dccg *dccg) in dcn201_clk_mgr_construct() argument
192 clk_mgr->dccg = dccg; in dcn201_clk_mgr_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.h | 33 struct dccg *dccg);
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| H A D | dcn316_clk_mgr.h | 45 struct dccg *dccg);
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| H A D | rn_clk_mgr.h | 47 struct dccg *dccg);
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| H A D | vg_clk_mgr.h | 48 struct dccg *dccg);
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/ |
| H A D | dcn201_hwseq.c | 234 if (res_pool->dccg->funcs->dccg_init) in dcn201_init_hw()
235 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn201_init_hw()
247 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, in dcn201_init_hw()
370 …if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gati… in dcn201_init_hw()
371 dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true); in dcn201_init_hw()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| H A D | dcn31_clk_mgr.h | 52 struct dccg *dccg);
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| H A D | dcn30_clk_mgr.h | 94 struct dccg *dccg);
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn21/ |
| H A D | dcn21_hwseq.c | 91 …if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->is_s0i3_golden_i… in dcn21_s0i3_golden_init_wa()
92 return !dc->res_pool->dccg->funcs->is_s0i3_golden_init_wa_done(dc->res_pool->dccg); in dcn21_s0i3_golden_init_wa()
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