| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn20/ |
| H A D | dcn20_dccg.c | 32 #define TO_DCN_DCCG(dccg)\ argument
33 container_of(dccg, struct dcn_dccg, base)
45 dccg->ctx->logger
47 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg2_update_dpp_dto() argument
49 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg2_update_dpp_dto()
51 if (dccg->ref_dppclk && req_dppclk) { in dccg2_update_dpp_dto()
52 int ref_dppclk = dccg->ref_dppclk; in dccg2_update_dpp_dto()
74 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; in dccg2_update_dpp_dto()
77 void dccg2_get_dccg_ref_freq(struct dccg *dccg, in dccg2_get_dccg_ref_freq() argument
81 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg2_get_dccg_ref_freq()
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn42/ |
| H A D | dcn42_dccg.c | 11 #define TO_DCN_DCCG(dccg)\ argument
12 container_of(dccg, struct dcn_dccg, base)
24 dccg->ctx->logger
26 void dccg42_otg_add_pixel(struct dccg *dccg, in dccg42_otg_add_pixel() argument
29 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg42_otg_add_pixel()
53 void dccg42_otg_drop_pixel(struct dccg *dccg, in dccg42_otg_drop_pixel() argument
56 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg42_otg_drop_pixel()
80 void dccg42_enable_global_fgcg(struct dccg *dccg, bool enable) in dccg42_enable_global_fgcg() argument
82 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg42_enable_global_fgcg()
87 …if (dccg->ctx->dc->debug.disable_clock_gate || (dccg->ctx->dc->debug.iommu_mismatch_temp_wka & 0x4… in dccg42_enable_global_fgcg()
[all …]
|
| H A D | dcn42_dccg.h | 244 void dccg42_otg_add_pixel(struct dccg *dccg,
247 void dccg42_otg_drop_pixel(struct dccg *dccg,
249 void dccg42_enable_global_fgcg(struct dccg *dccg, bool value);
250 bool dccg42_get_global_fgcg_status(struct dccg *dccg);
253 struct dccg *dccg,
259 struct dccg *dccg,
264 void dccg42_trigger_dio_fifo_resync(struct dccg *dccg);
266 struct dccg *dccg42_create(
|
| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn21/ |
| H A D | dcn21_dccg.c | 31 #define TO_DCN_DCCG(dccg)\ argument
32 container_of(dccg, struct dcn_dccg, base)
44 dccg->ctx->logger
46 static void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg21_update_dpp_dto() argument
48 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg21_update_dpp_dto()
50 if (dccg->ref_dppclk) { in dccg21_update_dpp_dto()
51 int ref_dppclk = dccg->ref_dppclk; in dccg21_update_dpp_dto()
96 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; in dccg21_update_dpp_dto()
114 static void dccg21_init(struct dccg *dccg) in dccg21_init() argument
116 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg21_init()
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/ |
| H A D | clk_mgr.c | 150 … clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg) in dc_clk_mgr_create() argument
224 rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
229 rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
251 dcn201_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
255 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
259 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
263 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
266 dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
277 vg_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
290 dcn31_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn60/ |
| H A D | dcn60_dccg.c | 10 #define TO_DCN_DCCG(dccg)\ argument
11 container_of(dccg, struct dcn_dccg, base)
23 dccg->ctx->logger
26 struct dccg *dccg, in dccg60_set_pixel_rate_div() argument
32 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg60_set_pixel_rate_div()
42 dccg401_get_pixel_rate_div(dccg, otg_inst, &cur_tmds_div, &dp_dto_int); in dccg60_set_pixel_rate_div()
72 static void dccg60_set_dto_dscclk(struct dccg *dccg, uint32_t inst, in dccg60_set_dto_dscclk() argument
75 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg60_set_dto_dscclk()
164 struct dccg *dccg60_create( in dccg60_create()
171 struct dccg *base; in dccg60_create()
|
| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn201/ |
| H A D | dcn201_dccg.c | 32 #define TO_DCN_DCCG(dccg)\ argument
33 container_of(dccg, struct dcn_dccg, base)
46 dccg->ctx->logger
48 static void dccg201_update_dpp_dto(struct dccg *dccg, int dpp_inst, in dccg201_update_dpp_dto() argument
67 struct dccg *dccg201_create( in dccg201_create()
74 struct dccg *base; in dccg201_create()
|
| H A D | dcn201_dccg.h | 31 struct dccg *dccg201_create(
|
| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn301/ |
| H A D | dcn301_dccg.c | 30 #define TO_DCN_DCCG(dccg)\ argument
31 container_of(dccg, struct dcn_dccg, base)
43 dccg->ctx->logger
58 struct dccg *dccg301_create( in dccg301_create()
65 struct dccg *base; in dccg301_create()
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_clk_mgr.h | 59 struct dccg *dccg);
66 struct dccg *dccg);
|
| H A D | dcn35_clk_mgr.c | 202 struct dccg *dccg = clk_mgr_internal->dccg; in dcn35_disable_otg_wa() local
233 has_active_hpo = dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(old_pipe) && in dcn35_disable_otg_wa()
234 dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(new_pipe); in dcn35_disable_otg_wa()
242 !dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe)) { in dcn35_disable_otg_wa()
260 struct dccg *dccg = clk_mgr->dccg; in dcn35_update_clocks_update_dtb_dto() local
277 dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { in dcn35_update_clocks_update_dtb_dto()
288 dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params); in dcn35_update_clocks_update_dtb_dto()
301 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; in dcn35_update_clocks_update_dpp_dto()
322 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i]; in dcn35_update_clocks_update_dpp_dto()
325 clk_mgr->dccg->funcs->update_dpp_dto( in dcn35_update_clocks_update_dpp_dto()
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| H A D | dcn20_clk_mgr.h | 29 void dcn2_update_clocks(struct clk_mgr *dccg,
44 struct dccg *dccg);
|
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn50/ |
| H A D | dcn50_hwseq.c | 92 struct dccg *dccg = dc->res_pool->dccg; in dcn50_update_dchubp_dpp() local
100 dccg->funcs->update_dpp_dto(dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz); in dcn50_update_dchubp_dpp()
264 struct dccg *dccg = dc->res_pool->dccg; in dcn50_update_dchubp_dpp_sequence() local
277 hwss_add_dccg_update_dpp_dto(seq_state, dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz); in dcn50_update_dchubp_dpp_sequence()
552 if (res_pool->dccg->funcs->dccg_init) in dcn50_init_hw()
553 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn50_init_hw()
576 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, in dcn50_init_hw()
721 …if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gati… in dcn50_init_hw()
722 dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true); in dcn50_init_hw()
|
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn60/ |
| H A D | dcn60_hwseq.c | 361 if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) { in dcn60_setup_audio_dto()
369 dc->res_pool->dccg->funcs->set_audio_dtbclk_dto( in dcn60_setup_audio_dto()
370 dc->res_pool->dccg, in dcn60_setup_audio_dto()
374 dc->res_pool->dccg->funcs->set_audio_dtbclk_dto( in dcn60_setup_audio_dto()
375 dc->res_pool->dccg, in dcn60_setup_audio_dto()
414 if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) { in dcn60_setup_audio_dto()
422 dc->res_pool->dccg->funcs->set_audio_dtbclk_dto( in dcn60_setup_audio_dto()
423 dc->res_pool->dccg, in dcn60_setup_audio_dto()
427 dc->res_pool->dccg->funcs->set_audio_dtbclk_dto( in dcn60_setup_audio_dto()
428 dc->res_pool->dccg, in dcn60_setup_audio_dto()
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/ |
| H A D | dcn201_clk_mgr.h | 32 struct dccg *dccg);
|
| H A D | dcn201_clk_mgr.c | 182 struct dccg *dccg) in dcn201_clk_mgr_construct() argument
192 clk_mgr->dccg = dccg; in dcn201_clk_mgr_construct()
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.h | 33 struct dccg *dccg);
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| H A D | dcn316_clk_mgr.h | 45 struct dccg *dccg);
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| H A D | rn_clk_mgr.h | 47 struct dccg *dccg);
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| H A D | vg_clk_mgr.h | 48 struct dccg *dccg);
|
| /linux/drivers/gpu/drm/amd/display/dc/pg/dcn42/ |
| H A D | dcn42_pg_cntl.c | 42 if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_get_global_fgcg_status) in pg_cntl42_save_and_disable_global_fgcg_rep()
43 …_rep_fgcg = pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_get_global_fgcg_status(pg_cntl->ctx->dc-… in pg_cntl42_save_and_disable_global_fgcg_rep()
47 if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg) in pg_cntl42_save_and_disable_global_fgcg_rep()
48 …pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg,… in pg_cntl42_save_and_disable_global_fgcg_rep()
59 if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg) in pg_cntl42_restore_global_fgcg_rep()
60 …pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg,… in pg_cntl42_restore_global_fgcg_rep()
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| H A D | dcn31_clk_mgr.h | 52 struct dccg *dccg);
|
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/ |
| H A D | dcn30_hwseq.c | 58 #define TO_DCN_DCCG(dccg)\ argument
59 container_of(dccg, struct dcn_dccg, base)
665 if (res_pool->dccg->funcs->dccg_init) in dcn30_init_hw()
666 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn30_init_hw()
697 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, in dcn30_init_hw()
813 …if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gati… in dcn30_init_hw()
814 dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true); in dcn30_init_hw()
959 (!dc->res_pool->dccg->funcs->enable_hdmicharclk)) in dcn30_setup_hdmi_frl_link()
1321 struct dccg *dccg = dc->res_pool->dccg; in dcn30_get_underflow_debug_data() local
1347 if (dccg) in dcn30_get_underflow_debug_data()
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| H A D | dcn30_clk_mgr.h | 94 struct dccg *dccg);
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/ |
| H A D | dcn60_clk_mgr.c | 187 clk_mgr->dccg->ref_dppclk = ref_dppclk_khz; in dcn60_update_clocks_update_dpp_dto()
208 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i]; in dcn60_update_clocks_update_dpp_dto()
211 clk_mgr->dccg->funcs->update_dpp_dto( in dcn60_update_clocks_update_dpp_dto()
212 clk_mgr->dccg, dpp_inst, dppclk_khz); in dcn60_update_clocks_update_dpp_dto()
247 struct dccg *dccg = clk_mgr->dccg; in dcn60_update_clocks_update_dtb_dto() local
263 use_hpo_encoder = dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(otg_master); in dcn60_update_clocks_update_dtb_dto()
272 dccg->ctx->dc->link_srv->dp_get_encoding_format( in dcn60_update_clocks_update_dtb_dto()
1595 struct dccg *dccg) in dcn60_clk_mgr_construct() argument
1611 clk_mgr->dccg = dccg; in dcn60_clk_mgr_construct()
|