| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/ |
| H A D | dcn32_hwseq.h | 48 void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context);
66 void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context);
68 void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context);
70 void dcn32_update_force_pstate(struct dc *dc, struct dc_state *context);
72 void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
78 void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, uns…
81 struct dc_state *context,
94 void dcn32_calculate_pix_rate_divider(struct dc *dc, struct dc_state *context, const struct dc_stre…
101 struct dc_state *context,
111 struct dc_state *context,
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| H A D | dcn20_hwseq.h | 39 struct dc_state *context);
42 struct dc_state *context);
57 void dcn20_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);
72 struct dc_state *context);
75 struct dc_state *context);
78 struct dc_state *context);
81 struct dc_state *context);
84 struct dc_state *context,
92 struct dc_state *context);
117 struct dc_state *context);
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/ |
| H A D | hw_sequencer.h | 38 struct dc_state;
193 struct dc_state *context;
266 struct dc_state *context;
330 struct dc_state *context;
457 struct dc_state *context;
1004 struct dc_state *context);
1006 struct dc_state *context);
1007 void (*disable_plane)(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);
1008 void (*disable_plane_sequence)(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx,
1013 int num_planes, struct dc_state *context);
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| H A D | dcn20_clk_mgr.h | 30 struct dc_state *context,
34 struct dc_state *context,
37 struct dc_state *context, bool safe_to_lower);
49 struct dc_state *context,
54 struct dc_state *context);
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| H A D | dcn20_clk_mgr.c | 105 struct dc_state *context, bool safe_to_lower) in dcn20_update_clocks_update_dpp_dto()
127 void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr, struct dc_state *context) in dcn20_update_clocks_update_dentist()
217 struct dc_state *context, in dcn2_update_clocks()
344 struct dc_state *context, in dcn2_update_clocks_fpga()
450 struct dc_state *context, in dcn2_get_clock()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/ |
| H A D | dce110_clk_mgr.h | 34 const struct dc_state *context,
40 struct dc_state *context);
42 uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context);
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| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_mst_types.c | 1187 struct dc_state *dc_state, in compute_mst_dsc_configs_for_link() argument
1209 …DRM_DEBUG_DRIVER("%s: MST_DSC Try to set up params from %d streams\n", __func__, dc_state->stream_… in compute_mst_dsc_configs_for_link()
1210 for (i = 0; i < dc_state->stream_count; i++) { in compute_mst_dsc_configs_for_link()
1213 stream = dc_state->streams[i]; in compute_mst_dsc_configs_for_link()
1352 struct dc_state *dc_state, in is_dsc_need_re_compute() argument
1376 …DRM_DEBUG_DRIVER("%s: MST_DSC check on %d streams in new dc_state\n", __func__, dc_state->stream_c… in is_dsc_need_re_compute()
1379 for (i = 0; i < dc_state->stream_count; i++) { in is_dsc_need_re_compute()
1383 stream = dc_state->streams[i]; in is_dsc_need_re_compute()
1483 struct dc_state *dc_state, in compute_mst_dsc_configs_for_state() argument
1495 for (i = 0; i < dc_state->stream_count; i++) in compute_mst_dsc_configs_for_state()
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| H A D | amdgpu_dm_plane.c | 1002 if (dm_plane_state_new->dc_state && in amdgpu_dm_plane_helper_prepare_fb()
1003 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) { in amdgpu_dm_plane_helper_prepare_fb()
1005 dm_plane_state_new->dc_state; in amdgpu_dm_plane_helper_prepare_fb()
1241 if (!dm_plane_state->dc_state) in amdgpu_dm_plane_atomic_check()
1258 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK) in amdgpu_dm_plane_atomic_check()
1435 if (!dm_plane_state || !dm_plane_state->dc_state) in amdgpu_dm_plane_panic_flush()
1438 dc_plane_state = dm_plane_state->dc_state; in amdgpu_dm_plane_panic_flush()
1492 if (old_dm_plane_state->dc_state) { in amdgpu_dm_plane_drm_plane_duplicate_state()
1493 dm_plane_state->dc_state = old_dm_plane_state->dc_state; in amdgpu_dm_plane_drm_plane_duplicate_state()
1494 dc_plane_state_retain(dm_plane_state->dc_state); in amdgpu_dm_plane_drm_plane_duplicate_state()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn314/ |
| H A D | dcn314_hwseq.h | 34 void dcn314_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
42 void dcn314_calculate_pix_rate_divider(struct dc *dc, struct dc_state *context, const struct dc_str…
44 void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, un…
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource_helpers.c | 92 struct dc_state *context) in dcn32_helper_calculate_num_ways_for_subvp()
108 struct dc_state *context) in dcn32_merge_pipes_for_subvp()
154 struct dc_state *context) in dcn32_all_pipes_have_stream_and_plane()
171 struct dc_state *context) in dcn32_subvp_in_use()
184 bool dcn32_mpo_in_use(struct dc_state *context) in dcn32_mpo_in_use()
196 bool dcn32_any_surfaces_rotated(struct dc *dc, struct dc_state *context) in dcn32_any_surfaces_rotated()
243 static void override_det_for_subvp(struct dc *dc, struct dc_state *context, uint8_t pipe_segments[]) in override_det_for_subvp()
312 struct dc_state *context, in dcn32_determine_det_override()
381 void dcn32_set_det_allocations(struct dc *dc, struct dc_state *context, in dcn32_set_det_allocations()
515 …cn32_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context) in dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/ |
| H A D | dcn401_clk_mgr.h | 56 struct dc_state *context;
62 struct dc_state *context;
67 struct dc_state *context;
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc_plane_priv.h | 33 uint8_t dc_plane_get_pipe_mask(struct dc_state *dc_state, const struct dc_plane_state *plane_state);
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn351/ |
| H A D | dcn351_hwseq.h | 32 void dcn351_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,
34 void dcn351_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,
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| H A D | dcn351_hwseq.c | 38 void dcn351_calc_blocks_to_gate(struct dc *dc, struct dc_state *context, in dcn351_calc_blocks_to_gate()
58 void dcn351_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context, in dcn351_calc_blocks_to_ungate()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/ |
| H A D | dce_clk_mgr.h | 37 struct dc_state *context);
39 uint32_t dce_get_max_pixel_clock_for_all_paths(struct dc_state *context);
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| /linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_dmc_wl.h | 28 u32 dc_state; member
33 void intel_dmc_wl_enable(struct intel_display *display, u32 dc_state);
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| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_clk_mgr.c | 184 static uint32_t get_max_pixel_clock_for_all_paths(struct dc_state *context) in get_max_pixel_clock_for_all_paths()
215 struct dc_state *context) in dce_get_required_clocks_state()
496 const struct dc_state *context, in dce110_fill_display_configs()
548 static uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context) in dce110_get_min_vblank_time_us()
600 struct dc_state *context) in dce_pplib_apply_display_requirements()
614 struct dc_state *context) in dce11_pplib_apply_display_requirements()
673 struct dc_state *context, in dce_update_clocks()
700 struct dc_state *context, in dce11_update_clocks()
727 struct dc_state *context, in dce112_update_clocks()
754 struct dc_state *context, in dce12_update_clocks()
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_resource.c | 121 static void start_new_topology_snapshot(struct dc *dc, struct dc_state *state) in start_new_topology_snapshot()
1742 struct dc_state *context) in resource_build_scaling_params_for_context()
2258 bool resource_is_pipe_topology_changed(const struct dc_state *state_a, in resource_is_pipe_topology_changed()
2259 const struct dc_state *state_b) in resource_is_pipe_topology_changed()
2419 static void resource_log_pipe_for_stream(struct dc *dc, struct dc_state *state, in resource_log_pipe_for_stream()
2457 static int resource_stream_to_stream_idx(struct dc_state *state, in resource_stream_to_stream_idx()
2477 void resource_log_pipe_topology_update(struct dc *dc, struct dc_state *state) in resource_log_pipe_topology_update()
2555 struct dc_state *context, in update_pipe_params_after_odm_slice_count_change()
2578 struct dc_state *context, in update_pipe_params_after_mpc_slice_count_change()
2842 static void swap_dio_link_enc_to_muxable_ctx(struct dc_state *context, in swap_dio_link_enc_to_muxable_ctx()
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| H A D | dc.c | 187 static int get_seamless_boot_stream_count(struct dc_state *ctx) in get_seamless_boot_stream_count()
1205 struct dc_state *context) in disable_all_writeback_pipes_for_stream()
1214 struct dc_state *context, in apply_ctx_interdependent_lock()
1238 static void dc_update_visual_confirm_color(struct dc *dc, struct dc_state *context, struct pipe_ctx… in dc_update_visual_confirm_color()
1324 static void disable_dangling_plane(struct dc *dc, struct dc_state *context) in disable_dangling_plane()
1327 struct dc_state *dangling_context = dc_state_create_current_copy(dc); in disable_dangling_plane()
1328 struct dc_state *current_ctx; in disable_dangling_plane()
1434 struct dc_state *context) in disable_vbios_mode_if_required()
1601 struct dc_state *ctx) in enable_timing_multisync()
1625 struct dc_state *ctx) in program_timing_sync()
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| H A D | dc_surface.c | 68 uint8_t dc_plane_get_pipe_mask(struct dc_state *dc_state, const struct dc_plane_state *plane_state) in dc_plane_get_pipe_mask() argument
74 struct pipe_ctx *pipe_ctx = &dc_state->res_ctx.pipe_ctx[i]; in dc_plane_get_pipe_mask()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 714 struct dc_state *context, in enable_stream_timing_calc()
754 struct dc_state *context, in dcn401_enable_stream_timing()
1235 static uint32_t dcn401_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx) in dcn401_calculate_cab_allocation()
1366 struct dc_state *context) in dcn401_prepare_bandwidth()
1425 struct dc_state *context) in dcn401_optimize_bandwidth()
1474 struct dc_state *context, in dcn401_dmub_hw_control_lock()
1509 void dcn401_fams2_update_config(struct dc *dc, struct dc_state *context, bool enable) in dcn401_fams2_update_config()
1521 static void update_dsc_for_odm_change(struct dc *dc, struct dc_state *context, in update_dsc_for_odm_change()
1560 void dcn401_update_odm(struct dc *dc, struct dc_state *context, in dcn401_update_odm()
1605 static void dcn401_add_dsc_sequence_for_odm_change(struct dc *dc, struct dc_state *context, in dcn401_add_dsc_sequence_for_odm_change()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.h | 36 struct dc_state *context, bool safe_to_lower);
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| H A D | dcn301_fpu.h | 37 struct dc_state *context,
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| /linux/arch/mips/mm/ |
| H A D | cerr-sb1.c | 445 struct dc_state { struct
450 static struct dc_state dc_states[] = { argument
466 struct dc_state *dsc = dc_states; in dc_state_str()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| H A D | dcn31_clk_mgr.h | 46 struct dc_state *context,
|