| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/ |
| H A D | dcn32_hwseq.h | 48 void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context);
66 void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context);
68 void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context);
70 void dcn32_update_force_pstate(struct dc *dc, struct dc_state *context);
72 void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
78 void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, uns…
81 struct dc_state *context,
94 void dcn32_calculate_pix_rate_divider(struct dc *dc, struct dc_state *context, const struct dc_stre…
101 struct dc_state *context,
111 struct dc_state *context,
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| H A D | dcn20_hwseq.h | 39 struct dc_state *context);
42 struct dc_state *context);
57 void dcn20_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);
72 struct dc_state *context);
75 struct dc_state *context);
78 struct dc_state *context);
81 struct dc_state *context);
84 struct dc_state *context,
92 struct dc_state *context);
117 struct dc_state *context);
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.h | 36 struct dc_state *context,
40 struct dc_state *context,
45 struct dc_state *context,
49 struct dc_state *context,
64 bool dcn20_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,
76 struct dc_state *context,
79 bool dcn21_validate_bandwidth_fp(struct dc *dc, struct dc_state *context, enum
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | dml2_dc_resource_mgmt.c | 58 static bool get_plane_id(struct dml2_context *dml2, const struct dc_state *state, const struct dc_p… in get_plane_id()
109 static struct pipe_ctx *find_master_pipe_of_stream(struct dml2_context *ctx, struct dc_state *state… in find_master_pipe_of_stream()
124 struct dc_state *state, unsigned int plane_id) in find_master_pipe_of_plane()
142 struct dc_state *state, unsigned int plane_id, unsigned int *pipes) in find_pipes_assigned_to_plane()
179 static bool validate_pipe_assignment(const struct dml2_context *ctx, const struct dc_state *state, … in validate_pipe_assignment()
247 static unsigned int find_preferred_pipe_candidates(const struct dc_state *existing_state, in find_preferred_pipe_candidates()
294 static unsigned int find_last_resort_pipe_candidates(const struct dc_state *existing_state, in find_last_resort_pipe_candidates()
346 struct dc_state *state, // The state we want to find a free mapping in in find_more_pipes_for_stream()
351 …const struct dc_state *existing_state) // The state (optional) that we want to minimize remapping … in find_more_pipes_for_stream()
415 struct dc_state *state, // The state we want to find a free mapping in in find_more_free_pipes()
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| H A D | dml2_wrapper_fpu.c | 160 …ate_lowest_supported_state_for_temp_read(struct dml2_context *dml2, struct dc_state *display_state, in calculate_lowest_supported_state_for_temp_read()
269 struct dc_state *display_state, in dml_mode_support_wrapper()
359 static bool call_dml_mode_support_and_programming(struct dc_state *context, enum dc_validate_mode v… in call_dml_mode_support_and_programming()
401 bool dml2_validate_and_build_resource(const struct dc *in_dc, struct dc_state *context, in dml2_validate_and_build_resource()
511 bool dml2_validate_only(struct dc_state *context, enum dc_validate_mode validate_mode) in dml2_validate_only()
558 void dml2_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_contex… in dml2_prepare_mcache_programming()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| H A D | dcn20_clk_mgr.h | 30 struct dc_state *context,
34 struct dc_state *context,
37 struct dc_state *context, bool safe_to_lower);
49 struct dc_state *context,
54 struct dc_state *context);
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| H A D | dcn20_clk_mgr.c | 105 struct dc_state *context, bool safe_to_lower) in dcn20_update_clocks_update_dpp_dto()
127 void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr, struct dc_state *context) in dcn20_update_clocks_update_dentist()
217 struct dc_state *context, in dcn2_update_clocks()
344 struct dc_state *context, in dcn2_update_clocks_fpga()
450 struct dc_state *context, in dcn2_get_clock()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.h | 38 void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);
39 void dcn315_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);
42 struct dc *dc, struct dc_state *context,
56 struct dc_state *context,
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/ |
| H A D | dce110_clk_mgr.h | 34 const struct dc_state *context,
40 struct dc_state *context);
42 uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context);
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| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_mst_types.c | 1187 struct dc_state *dc_state, in compute_mst_dsc_configs_for_link() argument
1209 …DRM_DEBUG_DRIVER("%s: MST_DSC Try to set up params from %d streams\n", __func__, dc_state->stream_… in compute_mst_dsc_configs_for_link()
1210 for (i = 0; i < dc_state->stream_count; i++) { in compute_mst_dsc_configs_for_link()
1213 stream = dc_state->streams[i]; in compute_mst_dsc_configs_for_link()
1352 struct dc_state *dc_state, in is_dsc_need_re_compute() argument
1376 …DRM_DEBUG_DRIVER("%s: MST_DSC check on %d streams in new dc_state\n", __func__, dc_state->stream_c… in is_dsc_need_re_compute()
1379 for (i = 0; i < dc_state->stream_count; i++) { in is_dsc_need_re_compute()
1383 stream = dc_state->streams[i]; in is_dsc_need_re_compute()
1483 struct dc_state *dc_state, in compute_mst_dsc_configs_for_state() argument
1495 for (i = 0; i < dc_state->stream_count; i++) in compute_mst_dsc_configs_for_state()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn314/ |
| H A D | dcn314_hwseq.h | 34 void dcn314_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
42 void dcn314_calculate_pix_rate_divider(struct dc *dc, struct dc_state *context, const struct dc_str…
44 void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, un…
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/ |
| H A D | dcn401_clk_mgr.h | 56 struct dc_state *context;
62 struct dc_state *context;
67 struct dc_state *context;
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/ |
| H A D | dml21_utils.c | 36 bool dml21_get_plane_id(const struct dc_state *state, const struct dc_plane_state *plane, unsigned … in dml21_get_plane_id()
85 struct dc_state *context, in dml21_find_dc_pipes_for_plane()
147 struct dc_state *context, in dml21_pipe_populate_global_sync()
163 void dml21_populate_mall_allocation_size(struct dc_state *context, in dml21_populate_mall_allocation_size()
197 static bool is_sub_vp_enabled(struct dc *dc, struct dc_state *context) in is_sub_vp_enabled()
213 void dml21_program_dc_pipe(struct dml2_context *dml_ctx, struct dc_state *context, struct pipe_ctx … in dml21_program_dc_pipe()
244 struct dc_state *context, in dml21_add_phantom_stream()
281 struct dc_state *context, in dml21_add_phantom_plane()
322 void dml21_handle_phantom_streams_planes(const struct dc *dc, struct dc_state *context, struct dml2… in dml21_handle_phantom_streams_planes()
381 struct dc_state *context, in dml21_build_fams2_stream_programming_v2()
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| H A D | dml21_wrapper_fpu.c | 51 static void dml21_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *context, struct… in dml21_calculate_rq_and_dlg_params()
141 static void dml21_prepare_mcache_params(struct dml2_context *dml_ctx, struct dc_state *context, str… in dml21_prepare_mcache_params()
170 static bool dml21_check_mode_support(const struct dc *in_dc, struct dc_state *context, struct dml2_… in dml21_check_mode_support()
199 static bool dml21_mode_check_and_programming(const struct dc *in_dc, struct dc_state *context, stru… in dml21_mode_check_and_programming()
259 bool dml21_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx, in dml21_validate()
273 void dml21_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_conte… in dml21_prepare_mcache_programming()
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc_plane_priv.h | 33 uint8_t dc_plane_get_pipe_mask(struct dc_state *dc_state, const struct dc_plane_state *plane_state);
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| H A D | dc_stream.h | 446 struct dc_state *state);
490 struct dc_state *state,
507 struct dc_state *context,
512 void dc_trigger_sync(struct dc *dc, struct dc_state *context);
550 struct dc_state *state,
640 struct dc_state *context);
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn351/ |
| H A D | dcn351_hwseq.h | 32 void dcn351_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,
34 void dcn351_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,
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| H A D | dcn351_hwseq.c | 38 void dcn351_calc_blocks_to_gate(struct dc *dc, struct dc_state *context, in dcn351_calc_blocks_to_gate()
58 void dcn351_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context, in dcn351_calc_blocks_to_ungate()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/ |
| H A D | dce_clk_mgr.h | 37 struct dc_state *context);
39 uint32_t dce_get_max_pixel_clock_for_all_paths(struct dc_state *context);
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| /linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_dmc_wl.h | 28 u32 dc_state; member
33 void intel_dmc_wl_enable(struct intel_display *display, u32 dc_state);
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_clk_mgr.h | 53 struct dc_state *context,
69 struct dc_state *context,
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_resource.c | 122 static void start_new_topology_snapshot(struct dc *dc, struct dc_state *state) in start_new_topology_snapshot()
1749 struct dc_state *context) in resource_build_scaling_params_for_context()
2268 bool resource_is_pipe_topology_changed(const struct dc_state *state_a, in resource_is_pipe_topology_changed()
2269 const struct dc_state *state_b) in resource_is_pipe_topology_changed()
2429 static void resource_log_pipe_for_stream(struct dc *dc, struct dc_state *state, in resource_log_pipe_for_stream()
2466 static int resource_stream_to_stream_idx(struct dc_state *state, in resource_stream_to_stream_idx()
2486 void resource_log_pipe_topology_update(struct dc *dc, struct dc_state *state) in resource_log_pipe_topology_update()
2564 struct dc_state *context, in update_pipe_params_after_odm_slice_count_change()
2587 struct dc_state *context, in update_pipe_params_after_mpc_slice_count_change()
2851 static void swap_dio_link_enc_to_muxable_ctx(struct dc_state *context, in swap_dio_link_enc_to_muxable_ctx()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn21/ |
| H A D | dcn21_hwseq.c | 99 struct dc_state *context) in dcn21_exit_optimized_pwr_state()
109 struct dc_state *context) in dcn21_optimize_pwr_state()
128 void dcn21_PLAT_58856_wa(struct dc_state *context, struct pipe_ctx *pipe_ctx) in dcn21_PLAT_58856_wa()
288 struct dc_state *context, struct dc_stream_state *stream) in dcn21_is_abm_supported()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | dcn32_fpu.c | 183 static bool dcn32_apply_merge_split_flags_helper(struct dc *dc, struct dc_state *context,
276 struct dc_state *context, in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
334 struct dc_state *context, in dcn32_helper_populate_phantom_dlg_params()
467 struct dc_state *context, in dcn32_set_phantom_stream_timing()
558 static unsigned int dcn32_get_num_free_pipes(struct dc *dc, struct dc_state *context) in dcn32_get_num_free_pipes()
600 struct dc_state *context, in dcn32_assign_subvp_pipe()
680 static bool dcn32_enough_pipes_for_subvp(struct dc *dc, struct dc_state *context) in dcn32_enough_pipes_for_subvp()
726 static bool subvp_subvp_schedulable(struct dc *dc, struct dc_state *context) in subvp_subvp_schedulable()
797 static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context) in subvp_drr_schedulable()
898 static bool subvp_vblank_schedulable(struct dc *dc, struct dc_state *context) in subvp_vblank_schedulable()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 612 struct dc_state *context, in enable_stream_timing_calc()
653 struct dc_state *context, in dcn401_enable_stream_timing()
1158 static uint32_t dcn401_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx) in dcn401_calculate_cab_allocation()
1289 struct dc_state *context) in dcn401_prepare_bandwidth()
1348 struct dc_state *context) in dcn401_optimize_bandwidth()
1397 struct dc_state *context, in dcn401_dmub_hw_control_lock()
1433 void dcn401_fams2_update_config(struct dc *dc, struct dc_state *context, bool enable) in dcn401_fams2_update_config()
1446 static void update_dsc_for_odm_change(struct dc *dc, struct dc_state *context, in update_dsc_for_odm_change()
1485 void dcn401_update_odm(struct dc *dc, struct dc_state *context, in dcn401_update_odm()
1530 static void dcn401_add_dsc_sequence_for_odm_change(struct dc *dc, struct dc_state *context, in dcn401_add_dsc_sequence_for_odm_change()
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