| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.h | 36 struct dc_state *context,
40 struct dc_state *context,
45 struct dc_state *context,
49 struct dc_state *context,
64 bool dcn20_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,
76 struct dc_state *context,
79 bool dcn21_validate_bandwidth_fp(struct dc *dc, struct dc_state *context, enum
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| H A D | dcn20_clk_mgr.h | 30 struct dc_state *context,
34 struct dc_state *context,
37 struct dc_state *context, bool safe_to_lower);
49 struct dc_state *context,
54 struct dc_state *context);
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | dml2_dc_resource_mgmt.c | 58 static bool get_plane_id(struct dml2_context *dml2, const struct dc_state *state, const struct dc_p… in get_plane_id()
109 static struct pipe_ctx *find_master_pipe_of_stream(struct dml2_context *ctx, struct dc_state *state… in find_master_pipe_of_stream()
124 struct dc_state *state, unsigned int plane_id) in find_master_pipe_of_plane()
142 struct dc_state *state, unsigned int plane_id, unsigned int *pipes) in find_pipes_assigned_to_plane()
179 static bool validate_pipe_assignment(const struct dml2_context *ctx, const struct dc_state *state, … in validate_pipe_assignment()
247 static unsigned int find_preferred_pipe_candidates(const struct dc_state *existing_state, in find_preferred_pipe_candidates()
294 static unsigned int find_last_resort_pipe_candidates(const struct dc_state *existing_state, in find_last_resort_pipe_candidates()
346 struct dc_state *state, // The state we want to find a free mapping in in find_more_pipes_for_stream()
351 …const struct dc_state *existing_state) // The state (optional) that we want to minimize remapping … in find_more_pipes_for_stream()
415 struct dc_state *state, // The state we want to find a free mapping in in find_more_free_pipes()
[all …]
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| H A D | dml2_wrapper_fpu.c | 160 …ate_lowest_supported_state_for_temp_read(struct dml2_context *dml2, struct dc_state *display_state, in calculate_lowest_supported_state_for_temp_read()
269 struct dc_state *display_state, in dml_mode_support_wrapper()
359 static bool call_dml_mode_support_and_programming(struct dc_state *context, enum dc_validate_mode v… in call_dml_mode_support_and_programming()
401 bool dml2_validate_and_build_resource(const struct dc *in_dc, struct dc_state *context, in dml2_validate_and_build_resource()
511 bool dml2_validate_only(struct dc_state *context, enum dc_validate_mode validate_mode) in dml2_validate_only()
558 void dml2_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_contex… in dml2_prepare_mcache_programming()
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| H A D | dml2_wrapper.c | 27 bool dml2_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml2, in dml2_validate()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.h | 38 void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);
39 void dcn315_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);
42 struct dc *dc, struct dc_state *context,
56 struct dc_state *context,
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/ |
| H A D | dce110_clk_mgr.h | 34 const struct dc_state *context,
40 struct dc_state *context);
42 uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context);
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn314/ |
| H A D | dcn314_hwseq.h | 34 void dcn314_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
42 void dcn314_calculate_pix_rate_divider(struct dc *dc, struct dc_state *context, const struct dc_str…
44 void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, un…
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc_plane_priv.h | 33 uint8_t dc_plane_get_pipe_mask(struct dc_state *dc_state, const struct dc_plane_state *plane_state);
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| H A D | Makefile | 77 FILES += core/dc_state.o
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn351/ |
| H A D | dcn351_hwseq.h | 32 void dcn351_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,
34 void dcn351_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_clk_mgr.h | 53 struct dc_state *context,
69 struct dc_state *context,
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| H A D | dcn35_clk_mgr.c | 158 struct dc_state *context, in dcn35_get_active_display_cnt_wa()
189 void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, in dcn35_disable_otg_wa()
257 struct dc_state *context, in dcn35_update_clocks_update_dtb_dto()
295 struct dc_state *context, bool safe_to_lower) in dcn35_update_clocks_update_dpp_dto()
355 static void dcn35_notify_host_router_bw(struct clk_mgr *clk_mgr_base, struct dc_state *context, in dcn35_notify_host_router_bw()
392 struct dc_state *context, in dcn35_update_clocks()
1217 struct dc_state *context = dc->current_state; in dcn35_set_low_power_state()
1251 struct dc_state *context, in dcn35_update_clocks_fpga()
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| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm.c | 146 STATIC_IFN_KUNIT void dm_enable_per_frame_crtc_master_sync(struct dc_state *context);
1409 struct dc_state *state, bool enable) in dm_gpureset_toggle_interrupts()
1461 DEFINE_FREE(state_release, struct dc_state *, if (_T) dc_state_release(_T)) in DEFINE_FREE() argument
1465 struct dc_state *context __free(state_release) = NULL; in DEFINE_FREE()
1554 if (dm_new_plane_state->dc_state) { in dm_destroy_cached_state()
1555 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1); in dm_destroy_cached_state()
1556 dc_plane_state_release(dm_new_plane_state->dc_state); in dm_destroy_cached_state()
1557 dm_new_plane_state->dc_state = NULL; in dm_destroy_cached_state()
1718 static void dm_gpureset_commit_state(struct dc_state *dc_state, in dm_gpureset_commit_state() argument
1737 for (k = 0; k < dc_state->stream_count; k++) { in dm_gpureset_commit_state()
[all …]
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| H A D | amdgpu_dm_plane.c | 1297 if (dm_plane_state_new->dc_state && in amdgpu_dm_plane_helper_prepare_fb()
1298 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) { in amdgpu_dm_plane_helper_prepare_fb()
1300 dm_plane_state_new->dc_state; in amdgpu_dm_plane_helper_prepare_fb()
1543 if (!dm_plane_state->dc_state) in amdgpu_dm_plane_atomic_check()
1568 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK) in amdgpu_dm_plane_atomic_check()
1764 if (!dm_plane_state || !dm_plane_state->dc_state) in amdgpu_dm_plane_panic_flush()
1767 dc_plane_state = dm_plane_state->dc_state; in amdgpu_dm_plane_panic_flush()
1822 if (old_dm_plane_state->dc_state) { in amdgpu_dm_plane_drm_plane_duplicate_state()
1823 dm_plane_state->dc_state = old_dm_plane_state->dc_state; in amdgpu_dm_plane_drm_plane_duplicate_state()
1824 dc_plane_state_retain(dm_plane_state->dc_state); in amdgpu_dm_plane_drm_plane_duplicate_state()
[all …]
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| H A D | amdgpu_dm_helpers.c | 1494 struct dc_state *dc_state = ctx->dc->current_state; in dm_helpers_dp_handle_test_pattern_request() local
1597 dc_state->bw_ctx.bw.dcn.clk.p_state_change_support = false; in dm_helpers_dp_handle_test_pattern_request()
1598 dc_state->bw_ctx.bw.dcn.clk.dramclk_khz = clk_mgr->dc_mode_softmax_enabled ? in dm_helpers_dp_handle_test_pattern_request()
1600 dc_state->bw_ctx.bw.dcn.clk.idle_dramclk_khz = dc_state->bw_ctx.bw.dcn.clk.dramclk_khz; in dm_helpers_dp_handle_test_pattern_request()
1603 dc_state, in dm_helpers_dp_handle_test_pattern_request()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.h | 36 struct dc_state *context, bool safe_to_lower);
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| H A D | dcn301_fpu.h | 37 struct dc_state *context,
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| H A D | dcn31_clk_mgr.h | 46 struct dc_state *context,
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| H A D | dcn31_clk_mgr.c | 78 struct dc_state *context) in dcn31_get_active_display_cnt_wa()
117 static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disab… in dcn31_disable_otg_wa()
138 struct dc_state *context, in dcn31_update_clocks()
645 struct dc_state *context = dc->current_state; in dcn31_set_low_power_state()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/ |
| H A D | dcn201_hwseq.h | 36 void dcn201_plane_atomic_disconnect(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ct…
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| /linux/arch/mips/mm/ |
| H A D | cerr-sb1.c | 445 struct dc_state { struct
450 static struct dc_state dc_states[] = { argument
466 struct dc_state *dsc = dc_states; in dc_state_str()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce100/ |
| H A D | dce100_resource.c | 850 struct dc_state *context, in build_mapped_resource()
868 struct dc_state *context, in dce100_validate_bandwidth()
909 struct dc_state *context) in dce100_validate_surface_sets()
930 struct dc_state *context) in dce100_validate_global()
941 struct dc_state *new_ctx, in dce100_add_stream_to_ctx()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/ |
| H A D | dcn201_clk_mgr.c | 85 struct dc_state *context, in dcn201_update_clocks()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| H A D | dcn314_clk_mgr.c | 112 struct dc_state *context) in dcn314_get_active_display_cnt_wa()
151 static void dcn314_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, in dcn314_disable_otg_wa()
209 struct dc_state *context, in dcn314_update_clocks()
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