Searched refs:dc_mode_limit (Results 1 – 7 of 7) sorted by relevance
| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/ |
| H A D | dml21_translation_helper.c | 111 if (config->use_clock_dc_limits && dc_bw_params->dc_mode_limit.dcfclk_mhz && in dml21_apply_soc_bb_overrides()
112 dc_clk_table->entries[i].dcfclk_mhz > dc_bw_params->dc_mode_limit.dcfclk_mhz) { in dml21_apply_soc_bb_overrides()
113 … if (i == 0 || dc_clk_table->entries[i-1].dcfclk_mhz < dc_bw_params->dc_mode_limit.dcfclk_mhz) { in dml21_apply_soc_bb_overrides()
114 dml_clk_table->dcfclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.dcfclk_mhz * 1000; in dml21_apply_soc_bb_overrides()
134 if (config->use_clock_dc_limits && dc_bw_params->dc_mode_limit.fclk_mhz && in dml21_apply_soc_bb_overrides()
135 dc_clk_table->entries[i].fclk_mhz > dc_bw_params->dc_mode_limit.fclk_mhz) { in dml21_apply_soc_bb_overrides()
136 if (i == 0 || dc_clk_table->entries[i-1].fclk_mhz < dc_bw_params->dc_mode_limit.fclk_mhz) { in dml21_apply_soc_bb_overrides()
137 dml_clk_table->fclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.fclk_mhz * 1000; in dml21_apply_soc_bb_overrides()
157 if (config->use_clock_dc_limits && dc_bw_params->dc_mode_limit.memclk_mhz && in dml21_apply_soc_bb_overrides()
158 dc_clk_table->entries[i].memclk_mhz > dc_bw_params->dc_mode_limit.memclk_mhz) { in dml21_apply_soc_bb_overrides()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/ |
| H A D | dcn401_clk_mgr.c | 240 …clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PP… in dcn401_init_clocks()
241 if (num_entries_per_clk->num_dcfclk_levels && clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz == in dcn401_init_clocks()
243 clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = 0; in dcn401_init_clocks()
249 …clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PP… in dcn401_init_clocks()
250 if (num_entries_per_clk->num_socclk_levels && clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz == in dcn401_init_clocks()
252 clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz = 0; in dcn401_init_clocks()
259 …clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PP… in dcn401_init_clocks()
260 if (num_entries_per_clk->num_dtbclk_levels && clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz == in dcn401_init_clocks()
262 clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz = 0; in dcn401_init_clocks()
269 …clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, P… in dcn401_init_clocks()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.c | 194 …clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PP… in dcn32_init_clocks()
200 …clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PP… in dcn32_init_clocks()
207 clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz = in dcn32_init_clocks()
216 …clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, P… in dcn32_init_clocks()
218 if (clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz > 1950) in dcn32_init_clocks()
219 clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = 1950; in dcn32_init_clocks()
226 …clk_mgr_base->bw_params->dc_mode_limit.dppclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PP… in dcn32_init_clocks()
228 if (clk_mgr_base->bw_params->dc_mode_limit.dppclk_mhz > 1950) in dcn32_init_clocks()
229 clk_mgr_base->bw_params->dc_mode_limit.dppclk_mhz = 1950; in dcn32_init_clocks()
1039 …clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PP… in dcn32_get_memclk_states_from_smu()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn321/ |
| H A D | dcn321_fpu.c | 382 if (bw_params->clk_table.entries[i].memclk_mhz <= bw_params->dc_mode_limit.memclk_mhz) in build_synthetic_soc_states()
387 if (bw_params->clk_table.entries[i].fclk_mhz <= bw_params->dc_mode_limit.fclk_mhz) in build_synthetic_soc_states()
392 if (bw_params->clk_table.entries[i].dcfclk_mhz <= bw_params->dc_mode_limit.dcfclk_mhz) in build_synthetic_soc_states()
399 override_max_clk_values(&bw_params->dc_mode_limit, &max_clk_data); in build_synthetic_soc_states()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | clk_mgr.h | 258 struct clk_limit_table_entry dc_mode_limit; member
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 231 …table.num_entries_per_clk.num_dcfclk_levels && dc->clk_mgr->bw_params->dc_mode_limit.dcfclk_mhz) || in dcn401_init_hw()
232 …ble.num_entries_per_clk.num_dispclk_levels && dc->clk_mgr->bw_params->dc_mode_limit.dispclk_mhz) || in dcn401_init_hw()
233 …table.num_entries_per_clk.num_dtbclk_levels && dc->clk_mgr->bw_params->dc_mode_limit.dtbclk_mhz) || in dcn401_init_hw()
234 …clk_table.num_entries_per_clk.num_fclk_levels && dc->clk_mgr->bw_params->dc_mode_limit.fclk_mhz) || in dcn401_init_hw()
235 …table.num_entries_per_clk.num_memclk_levels && dc->clk_mgr->bw_params->dc_mode_limit.memclk_mhz) || in dcn401_init_hw()
236 …k_table.num_entries_per_clk.num_socclk_levels && dc->clk_mgr->bw_params->dc_mode_limit.socclk_mhz); in dcn401_init_hw()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | dcn32_fpu.c | 2834 if (bw_params->clk_table.entries[i].memclk_mhz <= bw_params->dc_mode_limit.memclk_mhz) in build_synthetic_soc_states()
2839 if (bw_params->clk_table.entries[i].fclk_mhz <= bw_params->dc_mode_limit.fclk_mhz) in build_synthetic_soc_states()
2844 if (bw_params->clk_table.entries[i].dcfclk_mhz <= bw_params->dc_mode_limit.dcfclk_mhz) in build_synthetic_soc_states()
2851 override_max_clk_values(&bw_params->dc_mode_limit, &max_clk_data); in build_synthetic_soc_states()
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