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/linux/arch/m68k/ifpsp060/
H A Dpfpsp.sa1 dc.l $60ff0000,$17400000,$60ff0000,$15f40000
2 dc.l $60ff0000,$02b60000,$60ff0000,$04700000
3 dc.l $60ff0000,$1b100000,$60ff0000,$19aa0000
4 dc.l $60ff0000,$1b5a0000,$60ff0000,$062e0000
5 dc.l $60ff0000,$102c0000,$51fc51fc,$51fc51fc
6 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
7 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
8 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
9 dc.l $2f00203a,$ff2c487b,$0930ffff,$fef8202f
10 dc.l $00044e74,$00042f00,$203afef2,$487b0930
[all …]
H A Dfplsp.sa1 dc.l $60ff0000,$238e0000,$60ff0000,$24200000
2 dc.l $60ff0000,$24b60000,$60ff0000,$11060000
3 dc.l $60ff0000,$11980000,$60ff0000,$122e0000
4 dc.l $60ff0000,$0f160000,$60ff0000,$0fa80000
5 dc.l $60ff0000,$103e0000,$60ff0000,$12ae0000
6 dc.l $60ff0000,$13400000,$60ff0000,$13d60000
7 dc.l $60ff0000,$05ae0000,$60ff0000,$06400000
8 dc.l $60ff0000,$06d60000,$60ff0000,$213e0000
9 dc.l $60ff0000,$21d00000,$60ff0000,$22660000
10 dc.l $60ff0000,$16160000,$60ff0000,$16a80000
[all …]
H A Ditest.sa1 dc.l $60ff0000,$005c5465,$7374696e,$67203638
2 dc.l $30363020,$49535020,$73746172,$7465643a
3 dc.l $0a007061,$73736564,$0a002066,$61696c65
4 dc.l $640a0000,$4a80660e,$487affe8,$61ff0000
5 dc.l $4f9a588f,$4e752f01,$61ff0000,$4fa4588f
6 dc.l $487affd8,$61ff0000,$4f82588f,$4e754e56
7 dc.l $ff6048e7,$3f3c487a,$ff9e61ff,$00004f6c
8 dc.l $588f42ae,$ff78487b,$01700000,$00ea61ff
9 dc.l $00004f58,$588f61ff,$000000f0,$61ffffff
10 dc.l $ffa642ae,$ff78487b,$01700000,$0af661ff
[all …]
H A Dftest.sa1 dc.l $60ff0000,$00d40000,$60ff0000,$016c0000
2 dc.l $60ff0000,$01a80000,$54657374,$696e6720
3 dc.l $36383036,$30204650,$53502073,$74617274
4 dc.l $65643a0a,$00546573,$74696e67,$20363830
5 dc.l $36302046,$50535020,$756e696d,$706c656d
6 dc.l $656e7465,$6420696e,$73747275,$6374696f
7 dc.l $6e207374,$61727465,$643a0a00,$54657374
8 dc.l $696e6720,$36383036,$30204650,$53502065
9 dc.l $78636570,$74696f6e,$20656e61,$626c6564
10 dc.l $20737461,$72746564,$3a0a0070,$61737365
[all …]
H A Dilsp.sa1 dc.l $60ff0000,$01fe0000,$60ff0000,$02080000
2 dc.l $60ff0000,$04900000,$60ff0000,$04080000
3 dc.l $60ff0000,$051e0000,$60ff0000,$053c0000
4 dc.l $60ff0000,$055a0000,$60ff0000,$05740000
5 dc.l $60ff0000,$05940000,$60ff0000,$05b40000
6 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
7 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
8 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
9 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
10 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
[all …]
/linux/drivers/dma/
H A Dtxx9dmac.c24 static struct txx9dmac_cregs __iomem *__dma_regs(const struct txx9dmac_chan *dc) in __dma_regs() argument
26 return dc->ch_regs; in __dma_regs()
30 const struct txx9dmac_chan *dc) in __dma_regs32() argument
32 return dc->ch_regs; in __dma_regs32()
35 #define channel64_readq(dc, name) \ argument
36 __raw_readq(&(__dma_regs(dc)->name))
37 #define channel64_writeq(dc, name, val) \ argument
38 __raw_writeq((val), &(__dma_regs(dc)->name))
39 #define channel64_readl(dc, name) \ argument
40 __raw_readl(&(__dma_regs(dc)->name))
[all …]
/linux/drivers/tty/
H A Dnozomi.c315 struct nozomi *dc; member
463 static void nozomi_setup_memory(struct nozomi *dc) in nozomi_setup_memory() argument
465 void __iomem *offset = dc->base_addr + dc->config_table.dl_start; in nozomi_setup_memory()
472 dc->port[PORT_MDM].dl_addr[CH_A] = offset; in nozomi_setup_memory()
473 dc->port[PORT_MDM].dl_addr[CH_B] = in nozomi_setup_memory()
474 (offset += dc->config_table.dl_mdm_len1); in nozomi_setup_memory()
475 dc->port[PORT_MDM].dl_size[CH_A] = in nozomi_setup_memory()
476 dc->config_table.dl_mdm_len1 - buff_offset; in nozomi_setup_memory()
477 dc->port[PORT_MDM].dl_size[CH_B] = in nozomi_setup_memory()
478 dc->config_table.dl_mdm_len2 - buff_offset; in nozomi_setup_memory()
[all …]
/linux/drivers/md/
H A Ddm-delay.c59 struct delay_c *dc = timer_container_of(dc, t, delay_timer); in handle_delayed_timer() local
61 queue_work(dc->kdelayd_wq, &dc->flush_expired_bios); in handle_delayed_timer()
64 static void queue_timeout(struct delay_c *dc, unsigned long expires) in queue_timeout() argument
66 timer_reduce(&dc->delay_timer, expires); in queue_timeout()
69 static inline bool delay_is_fast(struct delay_c *dc) in delay_is_fast() argument
71 return !!dc->worker; in delay_is_fast()
86 static void flush_delayed_bios(struct delay_c *dc, bool flush_all) in flush_delayed_bios() argument
95 mutex_lock(&dc->process_bios_lock); in flush_delayed_bios()
96 spin_lock(&dc->delayed_bios_lock); in flush_delayed_bios()
97 list_replace_init(&dc->delayed_bios, &local_list); in flush_delayed_bios()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc.c95 dc->ctx
98 dc->ctx->logger
165 static void destroy_links(struct dc *dc) in destroy_links() argument
169 for (i = 0; i < dc->link_count; i++) { in destroy_links()
170 if (NULL != dc->links[i]) in destroy_links()
171 dc->link_srv->destroy_link(&dc->links[i]); in destroy_links()
202 struct dc *dc, in create_links() argument
207 struct dc_bios *bios = dc->ctx->dc_bios; in create_links()
209 dc->link_count = 0; in create_links()
239 for (i = 0; dc->link_count < connectors_num && i < MAX_LINKS; i++) { in create_links()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn50/
H A Ddcn50_hwseq.c47 dc->ctx->logger
53 static void dcn50_initialize_min_clocks(struct dc *dc) in dcn50_initialize_min_clocks() argument
55 struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk; in dcn50_initialize_min_clocks()
58 clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000; in dcn50_initialize_min_clocks()
59 clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000; in dcn50_initialize_min_clocks()
60 clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000; in dcn50_initialize_min_clocks()
61 clocks->dppclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dppclk_mhz * 1000; in dcn50_initialize_min_clocks()
62 if (dc->debug.disable_boot_optimizations) { in dcn50_initialize_min_clocks()
63 clocks->dispclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz * 1000; in dcn50_initialize_min_clocks()
70 if (dc->clk_mgr->funcs->get_dispclk_from_dentist) in dcn50_initialize_min_clocks()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn60/
H A Ddcn60_hwseq.c49 dc->ctx->logger
179 struct dc *dc) in dcn60_apply_single_controller_ctx_to_hw() argument
186 struct dce_hwseq *hws = dc->hwseq; in dcn60_apply_single_controller_ctx_to_hw()
191 hws->funcs.disable_stream_gating(dc, pipe_ctx); in dcn60_apply_single_controller_ctx_to_hw()
209 if (dc->config.disable_hbr_audio_dp2) in dcn60_apply_single_controller_ctx_to_hw()
211 dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) in dcn60_apply_single_controller_ctx_to_hw()
216 if (!pipe_ctx->stream->apply_seamless_boot_optimization && dc->config.use_pipe_ctx_sync_logic) in dcn60_apply_single_controller_ctx_to_hw()
217 check_syncd_pipes_for_disabled_master_pipe(dc, context, pipe_ctx->pipe_idx); in dcn60_apply_single_controller_ctx_to_hw()
249 if (!(hws->wa.dp_hpo_and_otg_sequence && dc->link_srv->dp_is_128b_132b_signal(pipe_ctx))) in dcn60_apply_single_controller_ctx_to_hw()
253 hws->funcs.enable_stream_timing(pipe_ctx, context, dc); in dcn60_apply_single_controller_ctx_to_hw()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/
H A DMakefile47 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)
48 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_vba.o := $(dml_ccflags)
49 CFLAGS_$(AMDDALPATH)/dc/dml/dcn10/dcn10_fpu.o := $(dml_ccflags)
50 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/dcn20_fpu.o := $(dml_ccflags)
51 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20.o := $(dml_ccflags) $(frame_warn_flag)
52 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20.o := $(dml_ccflags)
53 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20v2.o := $(dml_ccflags) $(frame_warn_flag)
54 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20v2.o := $(dml_ccflags)
55 CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_mode_vba_21.o := $(dml_ccflags) $(frame_warn_flag)
56 CFLAGS_$(AMDDALPATH)/dc/dm
[all...]
/linux/drivers/gpu/drm/tegra/
H A Ddc.c148 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset) in tegra_dc_readl_active() argument
152 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
153 value = tegra_dc_readl(dc, offset); in tegra_dc_readl_active()
154 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
177 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset); in tegra_plane_offset()
185 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset)); in tegra_plane_readl()
191 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset)); in tegra_plane_writel()
194 bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev) in tegra_dc_has_output() argument
196 struct device_node *np = dc->dev->of_node; in tegra_dc_has_output()
221 void tegra_dc_commit(struct tegra_dc *dc) in tegra_dc_commit() argument
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
H A Ddcn30_hwseq.c68 dc->ctx->logger
75 void dcn30_log_color_state(struct dc *dc, in dcn30_log_color_state() argument
79 struct dc_context *dc_ctx = dc->ctx; in dcn30_log_color_state()
80 struct resource_pool *pool = dc->res_pool; in dcn30_log_color_state()
161 dc->caps.color.dpp.input_lut_shared, in dcn30_log_color_state()
162 dc->caps.color.dpp.icsc, in dcn30_log_color_state()
163 dc->caps.color.dpp.dgam_ram, in dcn30_log_color_state()
164 dc->caps.color.dpp.dgam_rom_caps.srgb, in dcn30_log_color_state()
165 dc->caps.color.dpp.dgam_rom_caps.bt2020, in dcn30_log_color_state()
166 dc->caps.color.dpp.dgam_rom_caps.gamma2_2, in dcn30_log_color_state()
[all …]
/linux/drivers/scsi/esas2r/
H A Desas2r_disc.c291 struct esas2r_disc_context *dc = &a->disc_ctx; in esas2r_disc_queue_event() local
298 dc->disc_evt |= disc_evt; in esas2r_disc_queue_event()
314 struct esas2r_disc_context *dc = &a->disc_ctx; in esas2r_disc_start_port() local
326 if (dc->disc_evt) { in esas2r_disc_start_port()
352 esas2r_trace("disc_evt: %d", dc->disc_evt); in esas2r_disc_start_port()
354 dc->flags = 0; in esas2r_disc_start_port()
357 dc->flags |= DCF_POLLED; in esas2r_disc_start_port()
359 rq->interrupt_cx = dc; in esas2r_disc_start_port()
363 if (dc->disc_evt & DCDE_DEV_SCAN) { in esas2r_disc_start_port()
364 dc->disc_evt &= ~DCDE_DEV_SCAN; in esas2r_disc_start_port()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.h31 void dcn20_populate_dml_writeback_from_context(struct dc *dc,
39 void dcn20_calculate_dlg_params(struct dc *dc,
44 int dcn20_populate_dml_pipes_from_context(struct dc *dc,
48 void dcn20_calculate_wm(struct dc *dc,
57 void dcn20_update_bounding_box(struct dc *dc,
62 void dcn20_patch_bounding_box(struct dc *dc,
64 bool dcn20_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,
75 int dcn21_populate_dml_pipes_from_context(struct dc *dc,
79 bool dcn21_validate_bandwidth_fp(struct dc *dc, struct dc_state *context, enum
81 void dcn21_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);
[all …]
/linux/drivers/clk/mvebu/
H A Ddove-divider.c51 static unsigned int dove_get_divider(struct dove_clk *dc) in dove_get_divider() argument
56 val = readl_relaxed(dc->base + DIV_CTRL0); in dove_get_divider()
57 val >>= dc->div_bit_start; in dove_get_divider()
59 divider = val & ~(~0 << dc->div_bit_size); in dove_get_divider()
61 if (dc->divider_table) in dove_get_divider()
62 divider = dc->divider_table[divider]; in dove_get_divider()
67 static int dove_calc_divider(const struct dove_clk *dc, unsigned long rate, in dove_calc_divider() argument
74 if (dc->divider_table) { in dove_calc_divider()
77 for (i = 0; dc->divider_table[i]; i++) in dove_calc_divider()
78 if (divider == dc->divider_table[i]) { in dove_calc_divider()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn42b/
H A Ddcn42b_resource.c892 ctx->dc->caps.extended_aux_timeout_support); in dcn42b_aux_engine_create()
1642 struct dc *dc = pool->base.oem_device->ctx->dc; in dcn42b_resource_destruct() local
1644 dc->link_srv->destroy_ddc_service(&pool->base.oem_device); in dcn42b_resource_destruct()
1660 if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment) in dcn42b_build_pipe_pix_clk_params()
1699 …if (pixel_clk_params->requested_pix_clk_100hz > (uint32_t)(4 * stream->ctx->dc->clk_mgr->dprefclk_… in dcn42b_build_pipe_pix_clk_params()
1701 …} else if (pixel_clk_params->requested_pix_clk_100hz > (uint32_t)(2 * stream->ctx->dc->clk_mgr->dp… in dcn42b_build_pipe_pix_clk_params()
1703 …} else if (pixel_clk_params->requested_pix_clk_100hz > (uint32_t)(stream->ctx->dc->clk_mgr->dprefc… in dcn42b_build_pipe_pix_clk_params()
1744 ctx->dc->debug.enable_fine_grain_clock_gating.bits.mmhubbub); in dcn42b_mmhubbub_init()
1796 dsc401_set_fgcg(dsc, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc); in dcn42b_dsc_create()
1815 static void dcn42b_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) in dcn42b_update_bw_bounding_box_fpu() argument
[all …]
/linux/drivers/gpu/drm/verisilicon/
H A Dvs_cursor_plane.c52 struct vs_dc *dc; in vs_cursor_plane_atomic_check() local
70 dc = vcrtc->dc; in vs_cursor_plane_atomic_check()
75 new_plane_state->crtc_w > dc->identity.max_cursor_size) in vs_cursor_plane_atomic_check()
94 static void vs_cursor_plane_commit(struct vs_dc *dc, unsigned int output) in vs_cursor_plane_commit() argument
96 regmap_set_bits(dc->regs, VSDC_CURSOR_CONFIG(output), in vs_cursor_plane_commit()
109 struct vs_dc *dc = vcrtc->dc; in vs_cursor_plane_atomic_enable() local
111 regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), in vs_cursor_plane_atomic_enable()
115 vs_cursor_plane_commit(dc, output); in vs_cursor_plane_atomic_enable()
126 struct vs_dc *dc = vcrtc->dc; in vs_cursor_plane_atomic_disable() local
128 regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), in vs_cursor_plane_atomic_disable()
[all …]
H A Dvs_primary_plane.c56 static void vs_primary_plane_commit(struct vs_dc *dc, unsigned int output) in vs_primary_plane_commit() argument
58 regmap_set_bits(dc->regs, VSDC_FB_CONFIG_EX(output), in vs_primary_plane_commit()
70 struct vs_dc *dc = vcrtc->dc; in vs_primary_plane_atomic_enable() local
72 regmap_set_bits(dc->regs, VSDC_FB_CONFIG_EX(output), in vs_primary_plane_atomic_enable()
74 regmap_update_bits(dc->regs, VSDC_FB_CONFIG_EX(output), in vs_primary_plane_atomic_enable()
78 vs_primary_plane_commit(dc, output); in vs_primary_plane_atomic_enable()
89 struct vs_dc *dc = vcrtc->dc; in vs_primary_plane_atomic_disable() local
91 regmap_set_bits(dc->regs, VSDC_FB_CONFIG_EX(output), in vs_primary_plane_atomic_disable()
94 vs_primary_plane_commit(dc, output); in vs_primary_plane_atomic_disable()
105 struct vs_dc *dc; in vs_primary_plane_atomic_update() local
[all …]
/linux/drivers/md/bcache/
H A Dwriteback.h78 static inline bool bcache_dev_stripe_dirty(struct cached_dev *dc, in bcache_dev_stripe_dirty() argument
82 int stripe = offset_to_stripe(&dc->disk, offset); in bcache_dev_stripe_dirty()
88 if (atomic_read(dc->disk.stripe_sectors_dirty + stripe)) in bcache_dev_stripe_dirty()
91 if (nr_sectors <= dc->disk.stripe_size) in bcache_dev_stripe_dirty()
94 nr_sectors -= dc->disk.stripe_size; in bcache_dev_stripe_dirty()
102 static inline bool should_writeback(struct cached_dev *dc, struct bio *bio, in should_writeback() argument
105 unsigned int in_use = dc->disk.c->gc_stats.in_use; in should_writeback()
108 test_bit(BCACHE_DEV_DETACHING, &dc->disk.flags) || in should_writeback()
115 if (dc->partial_stripes_expensive && in should_writeback()
116 bcache_dev_stripe_dirty(dc, bio->bi_iter.bi_sector, in should_writeback()
[all …]
/linux/drivers/gpu/ipu-v3/
H A Dipu-dc.c109 static void dc_link_event(struct ipu_dc *dc, int event, int addr, int priority) in dc_link_event() argument
113 reg = readl(dc->base + DC_RL_CH(event)); in dc_link_event()
116 writel(reg, dc->base + DC_RL_CH(event)); in dc_link_event()
119 static void dc_write_tmpl(struct ipu_dc *dc, int word, u32 opcode, u32 operand, in dc_write_tmpl() argument
122 struct ipu_dc_priv *priv = dc->priv; in dc_write_tmpl()
160 int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced, in ipu_dc_init_sync() argument
163 struct ipu_dc_priv *priv = dc->priv; in ipu_dc_init_sync()
168 dc->di = ipu_di_get_num(di); in ipu_dc_init_sync()
186 if (dc->di) in ipu_dc_init_sync()
192 dc_link_event(dc, DC_EVT_NL, addr, 3); in ipu_dc_init_sync()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/
H A Ddcn401_resource.c835 ctx->dc->caps.extended_aux_timeout_support); in dcn401_aux_engine_create()
1449 static unsigned int dcn401_calc_num_avail_chans_for_mall(struct dc *dc, unsigned int num_chans) in dcn401_calc_num_avail_chans_for_mall() argument
1463 if (ASICREV_IS_GC_12_0_0_A0(dc->ctx->asic_id.hw_internal_rev)) { in dcn401_calc_num_avail_chans_for_mall()
1465 } else if (ASICREV_IS_GC_12_0_1_A0(dc->ctx->asic_id.hw_internal_rev)) { in dcn401_calc_num_avail_chans_for_mall()
1673 struct dc *dc = pool->base.oem_device->ctx->dc; in dcn401_resource_destruct() local
1675 dc->link_srv->destroy_ddc_service(&pool->base.oem_device); in dcn401_resource_destruct()
1758 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc); in dcn401_dsc_create()
1780 static void dcn401_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) in dcn401_update_bw_bounding_box_fpu() argument
1786 dc->caps.max_cab_allocation_bytes = dcn401_calc_num_avail_chans_for_mall( in dcn401_update_bw_bounding_box_fpu()
1787 dc, bw_params->num_channels) * in dcn401_update_bw_bounding_box_fpu()
[all …]
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/tests/
H A Damdgpu_dm_irq_test.c277 static struct dc *dm_test_alloc_dc_with_irq_service(struct kunit *test, in dm_test_alloc_dc_with_irq_service()
283 struct dc *dc; in dm_test_alloc_dc_with_irq_service() local
286 dc = dm_kunit_alloc_dc_with_ctx(test); in dm_test_alloc_dc_with_irq_service()
305 dc->res_pool = res_pool; in dm_test_alloc_dc_with_irq_service()
307 return dc; in dm_test_alloc_dc_with_irq_service()
1423 struct dc *dc; in dm_test_hpd_rx_irq_create_workqueue() local
1428 dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL); in dm_test_hpd_rx_irq_create_workqueue()
1429 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, dc); in dm_test_hpd_rx_irq_create_workqueue()
1430 dc->caps.max_links = 4; in dm_test_hpd_rx_irq_create_workqueue()
1431 adev->dm.dc = dc; in dm_test_hpd_rx_irq_create_workqueue()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.h38 void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);
39 void dcn315_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);
42 struct dc *dc, struct dc_state *context,
47 void dcn31_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);
48 void dcn315_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);
49 void dcn316_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);
55 int dcn31x_populate_dml_pipes_from_context(struct dc *dc,

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