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Searched refs:dc (Results 1 – 25 of 602) sorted by relevance

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/linux/arch/m68k/ifpsp060/
H A Dpfpsp.sa1 dc.l $60ff0000,$17400000,$60ff0000,$15f40000
2 dc.l $60ff0000,$02b60000,$60ff0000,$04700000
3 dc.l $60ff0000,$1b100000,$60ff0000,$19aa0000
4 dc.l $60ff0000,$1b5a0000,$60ff0000,$062e0000
5 dc.l $60ff0000,$102c0000,$51fc51fc,$51fc51fc
6 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
7 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
8 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
9 dc.l $2f00203a,$ff2c487b,$0930ffff,$fef8202f
10 dc.l $00044e74,$00042f00,$203afef2,$487b0930
[all …]
H A Dfplsp.sa1 dc.l $60ff0000,$238e0000,$60ff0000,$24200000
2 dc.l $60ff0000,$24b60000,$60ff0000,$11060000
3 dc.l $60ff0000,$11980000,$60ff0000,$122e0000
4 dc.l $60ff0000,$0f160000,$60ff0000,$0fa80000
5 dc.l $60ff0000,$103e0000,$60ff0000,$12ae0000
6 dc.l $60ff0000,$13400000,$60ff0000,$13d60000
7 dc.l $60ff0000,$05ae0000,$60ff0000,$06400000
8 dc.l $60ff0000,$06d60000,$60ff0000,$213e0000
9 dc.l $60ff0000,$21d00000,$60ff0000,$22660000
10 dc.l $60ff0000,$16160000,$60ff0000,$16a80000
[all …]
H A Ditest.sa1 dc.l $60ff0000,$005c5465,$7374696e,$67203638
2 dc.l $30363020,$49535020,$73746172,$7465643a
3 dc.l $0a007061,$73736564,$0a002066,$61696c65
4 dc.l $640a0000,$4a80660e,$487affe8,$61ff0000
5 dc.l $4f9a588f,$4e752f01,$61ff0000,$4fa4588f
6 dc.l $487affd8,$61ff0000,$4f82588f,$4e754e56
7 dc.l $ff6048e7,$3f3c487a,$ff9e61ff,$00004f6c
8 dc.l $588f42ae,$ff78487b,$01700000,$00ea61ff
9 dc.l $00004f58,$588f61ff,$000000f0,$61ffffff
10 dc.l $ffa642ae,$ff78487b,$01700000,$0af661ff
[all …]
H A Dftest.sa1 dc.l $60ff0000,$00d40000,$60ff0000,$016c0000
2 dc.l $60ff0000,$01a80000,$54657374,$696e6720
3 dc.l $36383036,$30204650,$53502073,$74617274
4 dc.l $65643a0a,$00546573,$74696e67,$20363830
5 dc.l $36302046,$50535020,$756e696d,$706c656d
6 dc.l $656e7465,$6420696e,$73747275,$6374696f
7 dc.l $6e207374,$61727465,$643a0a00,$54657374
8 dc.l $696e6720,$36383036,$30204650,$53502065
9 dc.l $78636570,$74696f6e,$20656e61,$626c6564
10 dc.l $20737461,$72746564,$3a0a0070,$61737365
[all …]
H A Dilsp.sa1 dc.l $60ff0000,$01fe0000,$60ff0000,$02080000
2 dc.l $60ff0000,$04900000,$60ff0000,$04080000
3 dc.l $60ff0000,$051e0000,$60ff0000,$053c0000
4 dc.l $60ff0000,$055a0000,$60ff0000,$05740000
5 dc.l $60ff0000,$05940000,$60ff0000,$05b40000
6 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
7 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
8 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
9 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
10 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/
H A Dhw_sequencer.h51 struct dc *dc; member
57 struct dc *dc; member
68 const struct dc *dc; member
74 struct dc *dc; member
79 struct dc *dc; member
107 struct dc *dc; member
113 struct dc *dc; member
145 const struct dc *dc; member
150 struct dc *dc; member
206 void (*hardware_release)(struct dc *dc);
[all …]
H A Dhw_sequencer_private.h75 void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
76 void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
77 void (*init_pipes)(struct dc *dc, struct dc_state *context);
78 void (*reset_hw_ctx_wrap)(struct dc *dc, struct dc_state *context);
79 void (*plane_atomic_disconnect)(struct dc *dc,
82 void (*update_mpcc)(struct dc *dc, struct pipe_ctx *pipe_ctx);
83 bool (*set_input_transfer_func)(struct dc *dc,
86 bool (*set_output_transfer_func)(struct dc *dc,
89 void (*power_down)(struct dc *dc);
92 bool (*enable_display_power_gating)(struct dc *dc,
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_hwseq.h32 struct dc;
34 void dcn10_hw_sequencer_construct(struct dc *dc);
38 struct dc *dc,
42 void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx);
46 struct dc *dc);
48 struct dc *dc,
51 struct dc *dc,
54 struct dc *dc,
57 void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock);
59 struct dc *dc,
[all …]
/linux/drivers/tty/
H A Dnozomi.c315 struct nozomi *dc; member
463 static void nozomi_setup_memory(struct nozomi *dc) in nozomi_setup_memory() argument
465 void __iomem *offset = dc->base_addr + dc->config_table.dl_start; in nozomi_setup_memory()
472 dc->port[PORT_MDM].dl_addr[CH_A] = offset; in nozomi_setup_memory()
473 dc->port[PORT_MDM].dl_addr[CH_B] = in nozomi_setup_memory()
474 (offset += dc->config_table.dl_mdm_len1); in nozomi_setup_memory()
475 dc->port[PORT_MDM].dl_size[CH_A] = in nozomi_setup_memory()
476 dc->config_table.dl_mdm_len1 - buff_offset; in nozomi_setup_memory()
477 dc->port[PORT_MDM].dl_size[CH_B] = in nozomi_setup_memory()
478 dc->config_table.dl_mdm_len2 - buff_offset; in nozomi_setup_memory()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.h31 void dcn20_log_color_state(struct dc *dc,
38 struct dc *dc,
41 struct dc *dc,
43 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);
44 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);
45 bool dcn20_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
47 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
49 void dcn20_program_output_csc(struct dc *dc,
57 void dcn20_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);
59 struct dc *dc,
[all …]
/linux/drivers/md/
H A Ddm-delay.c55 struct delay_c *dc = from_timer(dc, t, delay_timer); in handle_delayed_timer() local
57 queue_work(dc->kdelayd_wq, &dc->flush_expired_bios); in handle_delayed_timer()
60 static void queue_timeout(struct delay_c *dc, unsigned long expires) in queue_timeout() argument
62 timer_reduce(&dc->delay_timer, expires); in queue_timeout()
65 static inline bool delay_is_fast(struct delay_c *dc) in delay_is_fast() argument
67 return !!dc->worker; in delay_is_fast()
82 static void flush_delayed_bios(struct delay_c *dc, bool flush_all) in flush_delayed_bios() argument
91 mutex_lock(&dc->process_bios_lock); in flush_delayed_bios()
92 spin_lock(&dc->delayed_bios_lock); in flush_delayed_bios()
93 list_replace_init(&dc->delayed_bios, &local_list); in flush_delayed_bios()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
H A Ddcn32_hwseq.h31 struct dc;
44 bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable);
46 void dcn32_cab_for_ss_control(struct dc *dc, bool enable);
48 void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context);
53 bool dcn32_set_input_transfer_func(struct dc *dc,
60 bool dcn32_set_output_transfer_func(struct dc *dc,
64 void dcn32_init_hw(struct dc *dc);
66 void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context);
68 void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context);
70 void dcn32_update_force_pstate(struct dc *dc, struct dc_state *context);
[all …]
/linux/drivers/md/bcache/
H A Dwriteback.c30 static uint64_t __calc_target_rate(struct cached_dev *dc) in __calc_target_rate() argument
32 struct cache_set *c = dc->disk.c; in __calc_target_rate()
48 div64_u64(bdev_nr_sectors(dc->bdev) << WRITEBACK_SHARE_SHIFT, in __calc_target_rate()
52 div_u64(cache_sectors * dc->writeback_percent, 100); in __calc_target_rate()
61 static void __update_writeback_rate(struct cached_dev *dc) in __update_writeback_rate() argument
83 int64_t target = __calc_target_rate(dc); in __update_writeback_rate()
84 int64_t dirty = bcache_dev_sectors_dirty(&dc->disk); in __update_writeback_rate()
87 div_s64(error, dc->writeback_rate_p_term_inverse); in __update_writeback_rate()
101 struct cache_set *c = dc->disk.c; in __update_writeback_rate()
105 if (dc->writeback_consider_fragment && in __update_writeback_rate()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.h14 struct dc;
36 void dcn401_init_hw(struct dc *dc);
40 bool dcn401_set_output_transfer_func(struct dc *dc,
43 void dcn401_trigger_3dlut_dma_load(struct dc *dc,
50 struct dc *dc);
52 void dcn401_populate_mcm_luts(struct dc *dc,
64 bool dcn401_apply_idle_power_optimizations(struct dc *dc, bool enable);
66 struct ips_ono_region_state dcn401_read_ono_state(struct dc *dc,
68 void dcn401_wait_for_dcc_meta_propagation(const struct dc *dc,
71 void dcn401_prepare_bandwidth(struct dc *dc,
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
H A Ddcn35_hwseq.c76 static void enable_memory_low_power(struct dc *dc)
78 struct dce_hwseq *hws = dc->hwseq;
81 if (dc->debug.enable_mem_low_power.bits.dmcu) {
83 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) {
89 if (dc->debug.enable_mem_low_power.bits.optc) {
94 if (dc->debug.enable_mem_low_power.bits.vga) {
99 if (dc->debug.enable_mem_low_power.bits.mpc &&
100 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode)
101 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc);
103 …if (dc->debug.enable_mem_low_power.bits.vpg && dc->res_pool->stream_enc[0]->vpg->funcs->vpg_powerd…
[all …]
H A Ddcn35_hwseq.h32 struct dc;
34 void dcn35_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
48 void dcn35_init_hw(struct dc *dc);
54 void dcn35_power_down_on_boot(struct dc *dc);
56 bool dcn35_apply_idle_power_optimizations(struct dc *dc, bool enable);
58 void dcn35_z10_restore(const struct dc *dc);
60 void dcn35_init_pipes(struct dc *dc, struct dc_state *context);
61 void dcn35_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx);
62 void dcn35_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,
64 void dcn35_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn31/
H A Ddcn31_hwseq.c63 dc->ctx->logger
70 static void enable_memory_low_power(struct dc *dc) in enable_memory_low_power() argument
72 struct dce_hwseq *hws = dc->hwseq; in enable_memory_low_power()
75 if (dc->debug.enable_mem_low_power.bits.dmcu) { in enable_memory_low_power()
77 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) { in enable_memory_low_power()
83 if (dc->debug.enable_mem_low_power.bits.optc) { in enable_memory_low_power()
88 if (dc->debug.enable_mem_low_power.bits.vga) { in enable_memory_low_power()
93 if (dc->debug.enable_mem_low_power.bits.mpc && in enable_memory_low_power()
94 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode) in enable_memory_low_power()
95 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc); in enable_memory_low_power()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
H A Ddcn30_hwseq.c65 dc->ctx->logger
72 void dcn30_log_color_state(struct dc *dc, in dcn30_log_color_state() argument
75 struct dc_context *dc_ctx = dc->ctx; in dcn30_log_color_state()
76 struct resource_pool *pool = dc->res_pool; in dcn30_log_color_state()
147 dc->caps.color.dpp.input_lut_shared, in dcn30_log_color_state()
148 dc->caps.color.dpp.icsc, in dcn30_log_color_state()
149 dc->caps.color.dpp.dgam_ram, in dcn30_log_color_state()
150 dc->caps.color.dpp.dgam_rom_caps.srgb, in dcn30_log_color_state()
151 dc->caps.color.dpp.dgam_rom_caps.bt2020, in dcn30_log_color_state()
152 dc->caps.color.dpp.dgam_rom_caps.gamma2_2, in dcn30_log_color_state()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/calcs/
H A Ddcn_calcs.c40 dc->ctx->logger
318 if (pipe->plane_res.dpp->ctx->dc->debug.optimized_watermark) { in pipe_ctx_to_e2e_pipe_params()
333 input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs-> in pipe_ctx_to_e2e_pipe_params()
453 const struct dc *dc, in dcn_bw_calc_rq_dlg_ttu() argument
458 struct display_mode_lib *dml = (struct display_mode_lib *)(&dc->dml); in dcn_bw_calc_rq_dlg_ttu()
497 input->clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; in dcn_bw_calc_rq_dlg_ttu()
638 static bool dcn_bw_apply_registry_override(struct dc *dc) in dcn_bw_apply_registry_override() argument
642 if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc->debug.sr_exit_time_ns in dcn_bw_apply_registry_override()
643 && dc->debug.sr_exit_time_ns) { in dcn_bw_apply_registry_override()
645 dc->dcn_soc->sr_exit_time = dc->debug.sr_exit_time_ns / 1000.0; in dcn_bw_apply_registry_override()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn401/
H A Ddcn401_fpu.c16 double pstate_latency_us = clk_mgr->ctx->dc->dml.soc.dram_clock_change_latency_us; in dcn401_build_wm_range_table_fpu()
17 double fclk_change_latency_us = clk_mgr->ctx->dc->dml.soc.fclk_change_latency_us; in dcn401_build_wm_range_table_fpu()
18 double sr_exit_time_us = clk_mgr->ctx->dc->dml.soc.sr_exit_time_us; in dcn401_build_wm_range_table_fpu()
19 double sr_enter_plus_exit_time_us = clk_mgr->ctx->dc->dml.soc.sr_enter_plus_exit_time_us; in dcn401_build_wm_range_table_fpu()
24 uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz; in dcn401_build_wm_range_table_fpu()
62 if (clk_mgr->ctx->dc->bb_overrides.dummy_clock_change_latency_ns != 0x7FFFFFFF) { in dcn401_build_wm_range_table_fpu()
114 void dcn401_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) in dcn401_update_bw_bounding_box_fpu() argument
119 if (dc->bb_overrides.sr_exit_time_ns) in dcn401_update_bw_bounding_box_fpu()
120 dc->dml2_options.bbox_overrides.sr_exit_latency_us = in dcn401_update_bw_bounding_box_fpu()
121 dc->bb_overrides.sr_exit_time_ns / 1000.0; in dcn401_update_bw_bounding_box_fpu()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/
H A DMakefile39 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)
40 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_vba.o := $(dml_ccflags)
41 CFLAGS_$(AMDDALPATH)/dc/dml/dcn10/dcn10_fpu.o := $(dml_ccflags)
42 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/dcn20_fpu.o := $(dml_ccflags)
43 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20.o := $(dml_ccflags) $(frame_warn_flag)
44 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20.o := $(dml_ccflags)
45 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20v2.o := $(dml_ccflags) $(frame_warn_flag)
46 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20v2.o := $(dml_ccflags)
47 CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_mode_vba_21.o := $(dml_ccflags) $(frame_warn_flag)
48 CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_rq_dlg_calc_21.o := $(dml_ccflags)
[all …]
/linux/drivers/gpu/drm/tegra/
H A Ddc.c50 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset) in tegra_dc_readl_active() argument
54 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
55 value = tegra_dc_readl(dc, offset); in tegra_dc_readl_active()
56 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
79 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset); in tegra_plane_offset()
87 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset)); in tegra_plane_readl()
93 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset)); in tegra_plane_writel()
96 bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev) in tegra_dc_has_output() argument
98 struct device_node *np = dc->dev->of_node; in tegra_dc_has_output()
121 void tegra_dc_commit(struct tegra_dc *dc) in tegra_dc_commit() argument
[all …]
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_stream.c37 #define DC_LOGGER dc->ctx->logger
54 if (stream->ctx->dc->caps.dual_link_dvi && in update_stream_signal()
202 if (new_stream->ctx->dc->res_pool->funcs->link_encs_assign) in dc_copy_stream()
220 struct dc *dc = stream->ctx->dc; in dc_stream_get_status() local
221 return dc_state_get_stream_status(dc->current_state, stream); in dc_stream_get_status()
225 struct dc *dc, in program_cursor_attributes() argument
235 res_ctx = &dc->current_state->res_ctx; in program_cursor_attributes()
245 dc->hwss.cursor_lock(dc, pipe_to_program, true); in program_cursor_attributes()
247 dc->hwss.cursor_lock(dc, pipe_to_program->next_odm_pipe, true); in program_cursor_attributes()
250 dc->hwss.set_cursor_attribute(pipe_ctx); in program_cursor_attributes()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml2/
H A DMakefile38 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2
39 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/src/dml2_core
40 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/src/dml2_mcg/
41 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/src/dml2_dpmm/
42 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/src/dml2_pmo/
43 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/src/dml2_standalone_libraries/
44 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/src/inc
45 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/inc
46 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/
48 CFLAGS_$(AMDDALPATH)/dc/dml2/display_mode_core.o := $(dml2_ccflags) $(frame_warn_flag)
[all …]
/linux/drivers/scsi/esas2r/
H A Desas2r_disc.c291 struct esas2r_disc_context *dc = &a->disc_ctx; in esas2r_disc_queue_event() local
298 dc->disc_evt |= disc_evt; in esas2r_disc_queue_event()
314 struct esas2r_disc_context *dc = &a->disc_ctx; in esas2r_disc_start_port() local
326 if (dc->disc_evt) { in esas2r_disc_start_port()
352 esas2r_trace("disc_evt: %d", dc->disc_evt); in esas2r_disc_start_port()
354 dc->flags = 0; in esas2r_disc_start_port()
357 dc->flags |= DCF_POLLED; in esas2r_disc_start_port()
359 rq->interrupt_cx = dc; in esas2r_disc_start_port()
363 if (dc->disc_evt & DCDE_DEV_SCAN) { in esas2r_disc_start_port()
364 dc->disc_evt &= ~DCDE_DEV_SCAN; in esas2r_disc_start_port()
[all …]

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