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/linux/arch/riscv/kernel/
H A Dtraps_misaligned.c320 ulong data_ulong; member
451 SET_RD(insn, regs, val.data_ulong << shift >> shift); in handle_scalar_misaligned_load()
455 set_f32_rd(insn, regs, val.data_ulong); in handle_scalar_misaligned_load()
483 val.data_ulong = GET_RS2(insn, regs); in handle_scalar_misaligned_store()
498 val.data_ulong = GET_F32_RS2(insn, regs); in handle_scalar_misaligned_store()
504 val.data_ulong = GET_RS2S(insn, regs); in handle_scalar_misaligned_store()
507 val.data_ulong = GET_RS2C(insn, regs); in handle_scalar_misaligned_store()
511 val.data_ulong = GET_RS2S(insn, regs); in handle_scalar_misaligned_store()
514 val.data_ulong = GET_RS2C(insn, regs); in handle_scalar_misaligned_store()
527 val.data_ulong = GET_F32_RS2S(insn, regs); in handle_scalar_misaligned_store()
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