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/linux/drivers/staging/vme_user/
H A Dvme_fake.c49 u32 cycle; member
57 u32 cycle; member
156 dma_addr_t buf_base, u32 aspace, u32 cycle) in fake_slave_set() argument
213 bridge->slaves[i].cycle = cycle; in fake_slave_set()
225 dma_addr_t *buf_base, u32 *aspace, u32 *cycle) in fake_slave_get() argument
241 *cycle = bridge->slaves[i].cycle; in fake_slave_get()
253 u32 aspace, u32 cycle, u32 dwidth) in fake_master_set() argument
321 bridge->masters[i].cycle = cycle; in fake_master_set()
339 u32 *aspace, u32 *cycle, u32 *dwidth) in __fake_master_get() argument
352 *cycle = bridge->masters[i].cycle; in __fake_master_get()
[all …]
H A Dvme_tsi148.c468 dma_addr_t pci_base, u32 aspace, u32 cycle) in tsi148_slave_set() argument
554 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) { in tsi148_slave_set()
568 if (cycle & VME_BLT) in tsi148_slave_set()
570 if (cycle & VME_MBLT) in tsi148_slave_set()
572 if (cycle & VME_2eVME) in tsi148_slave_set()
574 if (cycle & VME_2eSST) in tsi148_slave_set()
576 if (cycle & VME_2eSSTB) in tsi148_slave_set()
584 if (cycle & VME_SUPER) in tsi148_slave_set()
586 if (cycle & VME_USER) in tsi148_slave_set()
588 if (cycle & VME_PROG) in tsi148_slave_set()
[all …]
H A Dvme.c137 u32 aspace, cycle, dwidth; in vme_get_size() local
142 &aspace, &cycle, &dwidth); in vme_get_size()
149 &buf_base, &aspace, &cycle); in vme_get_size()
252 u32 cycle) in vme_slave_request() argument
276 ((slave_image->cycle_attr & cycle) == cycle) && in vme_slave_request()
329 dma_addr_t buf_base, u32 aspace, u32 cycle) in vme_slave_set() argument
348 ((image->cycle_attr & cycle) == cycle))) { in vme_slave_set()
358 aspace, cycle); in vme_slave_set()
379 dma_addr_t *buf_base, u32 *aspace, u32 *cycle) in vme_slave_get() argument
397 aspace, cycle); in vme_slave_get()
[all …]
/linux/drivers/ata/
H A Dlibata-pata-timings.c70 q->cycle = EZ(t->cycle, T); in ata_timing_quantize()
92 m->cycle = max(a->cycle, b->cycle); in ata_timing_merge()
141 p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO]; in ata_timing_compute()
144 p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO_IORDY]; in ata_timing_compute()
146 p.cycle = id[ATA_ID_EIDE_DMA_MIN]; in ata_timing_compute()
177 if (t->active + t->recover < t->cycle) { in ata_timing_compute()
178 t->active += (t->cycle - (t->active + t->recover)) / 2; in ata_timing_compute()
179 t->recover = t->cycle - t->active; in ata_timing_compute()
187 if (t->active + t->recover > t->cycle) in ata_timing_compute()
188 t->cycle = t->active + t->recover; in ata_timing_compute()
H A Dpata_icside.c192 unsigned int cycle; in pata_icside_set_dmamode() local
205 if (t.active <= 50 && t.recover <= 375 && t.cycle <= 425) { in pata_icside_set_dmamode()
207 cycle = 187; in pata_icside_set_dmamode()
208 } else if (t.active <= 125 && t.recover <= 375 && t.cycle <= 500) { in pata_icside_set_dmamode()
210 cycle = 250; in pata_icside_set_dmamode()
211 } else if (t.active <= 200 && t.recover <= 550 && t.cycle <= 750) { in pata_icside_set_dmamode()
213 cycle = 437; in pata_icside_set_dmamode()
216 cycle = 562; in pata_icside_set_dmamode()
220 t.active, t.recover, t.cycle, iomd_type); in pata_icside_set_dmamode()
222 state->port[ap->port_no].speed[adev->devno] = cycle; in pata_icside_set_dmamode()
/linux/arch/alpha/lib/
H A Dev6-csum_ipv6_magic.S116 cmpult $20,$3,$3 # E : (1 cycle stall on $20)
117 addq $20,$18,$20 # E : U L U L (1 cycle stall on $20)
120 addq $20,$19,$20 # E : (1 cycle stall on $20)
125 addq $18,$19,$18 # E : (1 cycle stall on $19)
131 zapnot $0,15,$1 # U : Start folding output (1 cycle stall on $0)
133 srl $0,32,$0 # U : U L U L : (1 cycle stall on $0)
136 extwl $1,2,$2 # U : ushort[1] (1 cycle stall on $1)
137 zapnot $1,3,$0 # U : ushort[0] (1 cycle stall on $1)
138 extwl $1,4,$1 # U : ushort[2] (1 cycle stall on $1)
143 extwl $3,2,$1 # U : ushort[1] (1 cycle stall on $3)
[all …]
H A Dev6-memchr.S67 extqh $6, $16, $6 # U : 2 cycle stall for $6
107 cmoveq $1, $3, $0 # E : Latency 2, extra map cycle
110 addq $0, 2, $3 # E : U L U L : 2 cycle stall on $0
112 cmoveq $1, $3, $0 # E : Latency 2, extra map cycle
115 addq $0, 1, $3 # E : U L U L : 2 cycle stall on $0
117 cmoveq $1, $3, $0 # E : Latency 2, extra map cycle
/linux/scripts/
H A Dheaderdep.pl116 my $cycle = shift;
119 for my $i (0 .. $#$cycle - 1) {
120 $cycle->[$i]->[0] = $cycle->[$i + 1]->[0];
122 $cycle->[-1]->[0] = 0;
124 my $first = shift @$cycle;
125 my $last = pop @$cycle;
130 for my $header (reverse @$cycle) {
/linux/kernel/locking/
H A Dtest-ww_mutex.c290 struct test_cycle *cycle = container_of(work, typeof(*cycle), work); in test_cycle_work() local
295 ww_mutex_lock(&cycle->a_mutex, &ctx); in test_cycle_work()
297 complete(cycle->a_signal); in test_cycle_work()
298 wait_for_completion(&cycle->b_signal); in test_cycle_work()
300 err = ww_mutex_lock(cycle->b_mutex, &ctx); in test_cycle_work()
303 ww_mutex_unlock(&cycle->a_mutex); in test_cycle_work()
304 ww_mutex_lock_slow(cycle->b_mutex, &ctx); in test_cycle_work()
305 erra = ww_mutex_lock(&cycle->a_mutex, &ctx); in test_cycle_work()
309 ww_mutex_unlock(cycle->b_mutex); in test_cycle_work()
311 ww_mutex_unlock(&cycle->a_mutex); in test_cycle_work()
[all …]
/linux/drivers/clocksource/
H A Dtimer-atmel-pit.c43 u32 cycle; member
85 elapsed += PIT_PICNT(t) * data->cycle; in read_pit_clk()
95 pit_write(data->base, AT91_PIT_MR, (data->cycle - 1) | AT91_PIT_PITEN); in pit_clkevt_shutdown()
107 data->cnt += data->cycle * PIT_PICNT(pit_read(data->base, AT91_PIT_PIVR)); in pit_clkevt_set_periodic()
109 (data->cycle - 1) | AT91_PIT_PITEN | AT91_PIT_PITIEN); in pit_clkevt_set_periodic()
132 (data->cycle - 1) | AT91_PIT_PITEN); in at91sam926x_pit_reset()
153 data->cnt += data->cycle * PIT_PICNT(pit_read(data->base, in at91sam926x_pit_interrupt()
210 data->cycle = DIV_ROUND_CLOSEST(pit_rate, HZ); in at91sam926x_pit_dt_init()
211 WARN_ON(((data->cycle - 1) & ~AT91_PIT_PIV) != 0); in at91sam926x_pit_dt_init()
220 bits = 12 /* PICNT */ + ilog2(data->cycle) /* PIV */; in at91sam926x_pit_dt_init()
/linux/drivers/pwm/
H A Dpwm-sl28cpld.c129 unsigned int cycle, prescaler; in sl28cpld_pwm_apply() local
152 cycle = SL28CPLD_PWM_FROM_DUTY_CYCLE(state->duty_cycle); in sl28cpld_pwm_apply()
153 cycle = min_t(unsigned int, cycle, SL28CPLD_PWM_MAX_DUTY_CYCLE(prescaler)); in sl28cpld_pwm_apply()
163 if (cycle == SL28CPLD_PWM_MAX_DUTY_CYCLE(0)) { in sl28cpld_pwm_apply()
166 cycle = SL28CPLD_PWM_MAX_DUTY_CYCLE(1); in sl28cpld_pwm_apply()
181 ret = sl28cpld_pwm_write(priv, SL28CPLD_PWM_CYCLE, cycle); in sl28cpld_pwm_apply()
191 ret = sl28cpld_pwm_write(priv, SL28CPLD_PWM_CYCLE, cycle); in sl28cpld_pwm_apply()
/linux/tools/power/cpupower/bench/
H A Dbenchmark.c80 unsigned int _round, cycle; in start_benchmark() local
125 for (cycle = 0; cycle < config->cycles; cycle++) { in start_benchmark()
151 for (cycle = 0; cycle < config->cycles; cycle++) { in start_benchmark()
/linux/sound/firewire/
H A Damdtp-stream.c484 static unsigned int compute_syt_offset(unsigned int syt, unsigned int cycle, in compute_syt_offset() argument
487 unsigned int cycle_lo = (cycle % CYCLES_PER_SECOND) & 0x0f; in compute_syt_offset()
534 dst->syt_offset = compute_syt_offset(src->syt, src->cycle, transfer_delay); in cache_seq()
705 static void build_it_pkt_header(struct amdtp_stream *s, unsigned int cycle, in build_it_pkt_header() argument
725 trace_amdtp_packet(s, cycle, cip_header, payload_length + header_length, data_blocks, in build_it_pkt_header()
828 static int parse_ir_ctx_header(struct amdtp_stream *s, unsigned int cycle, in parse_ir_ctx_header() argument
877 trace_amdtp_packet(s, cycle, cip_header, payload_length, *data_blocks, in parse_ir_ctx_header()
897 static inline u32 increment_ohci_cycle_count(u32 cycle, unsigned int addend) in increment_ohci_cycle_count() argument
899 cycle += addend; in increment_ohci_cycle_count()
900 if (cycle >= OHCI_SECOND_MODULUS * CYCLES_PER_SECOND) in increment_ohci_cycle_count()
[all …]
/linux/Documentation/admin-guide/perf/
H A Dalibaba_pmu.rst27 pmu_cycle_cnt_low and pmu_cycle_cnt_high, that is used as the cycle count
61 -e ali_drw_21000/cycle/ \
65 -e ali_drw_21080/cycle/ \
69 -e ali_drw_23000/cycle/ \
73 -e ali_drw_23080/cycle/ \
77 -e ali_drw_25000/cycle/ \
81 -e ali_drw_25080/cycle/ \
85 -e ali_drw_27000/cycle/ \
89 -e ali_drw_27080/cycle/ -- sleep 10
/linux/Documentation/hwmon/
H A Ddme1737.rst167 cycle) of the input. The chip adjusts the sampling rate based on this value.
178 manual mode, the fan speed is set by writing the duty-cycle value to the
180 current duty-cycle as set by the fan controller in the chip. All PWM outputs
198 pwm[1-3]_auto_point2_pwm full-speed duty-cycle (255, i.e., 100%)
199 pwm[1-3]_auto_point1_pwm low-speed duty-cycle
200 pwm[1-3]_auto_pwm_min min-speed duty-cycle
208 The chip adjusts the output duty-cycle linearly in the range of auto_point1_pwm
211 auto_point1_temp_hyst value, the output duty-cycle is set to the auto_pwm_min
214 duty-cycle. If any of the temperatures rise above the auto_point3_temp value,
215 all PWM outputs are set to 100% duty-cycle.
[all …]
H A Dvt1211.rst196 pwm[1-2]_auto_point4_pwm full speed duty-cycle (hard-wired to 255)
197 pwm[1-2]_auto_point3_pwm high speed duty-cycle
198 pwm[1-2]_auto_point2_pwm low speed duty-cycle
199 pwm[1-2]_auto_point1_pwm off duty-cycle (hard-wired to 0)
212 PWM output duty-cycle based on the input temperature:
218 - full speed duty-cycle full speed duty-cycle
220 - high speed duty-cycle full speed duty-cycle
222 - low speed duty-cycle high speed duty-cycle
224 - off duty-cycle low speed duty-cycle
/linux/arch/mips/dec/
H A Dkn02xa-berr.c53 const char *kind, *agent, *cycle, *event; in dec_kn02xa_be_backend() local
72 cycle = mreadstr; in dec_kn02xa_be_backend()
75 cycle = invoker ? writestr : readstr; in dec_kn02xa_be_backend()
84 kind, agent, cycle, event, address); in dec_kn02xa_be_backend()
H A Dkn01-berr.c81 const char *kind, *agent, *cycle, *event; in dec_kn01_be_backend() local
126 cycle = mreadstr; in dec_kn01_be_backend()
129 cycle = invoker ? writestr : readstr; in dec_kn01_be_backend()
138 kind, agent, cycle, event, address); in dec_kn01_be_backend()
H A Decc-berr.c54 const char *kind, *agent, *cycle, *event; in dec_ecc_be_backend() local
81 cycle = (erraddr & KN0X_EAR_WRITE) ? mwritstr : mreadstr; in dec_ecc_be_backend()
85 cycle = (erraddr & KN0X_EAR_WRITE) ? writestr : readstr; in dec_ecc_be_backend()
185 kind, agent, cycle, event, address); in dec_ecc_be_backend()
/linux/drivers/mfd/
H A Datmel-smc.c229 conf->cycle &= ~GENMASK(shift + 15, shift); in atmel_smc_cs_conf_set_cycle()
230 conf->cycle |= val << shift; in atmel_smc_cs_conf_set_cycle()
250 regmap_write(regmap, ATMEL_SMC_CYCLE(cs), conf->cycle); in atmel_smc_cs_conf_apply()
271 regmap_write(regmap, ATMEL_HSMC_CYCLE(layout, cs), conf->cycle); in atmel_hsmc_cs_conf_apply()
291 regmap_read(regmap, ATMEL_SMC_CYCLE(cs), &conf->cycle); in atmel_smc_cs_conf_get()
312 regmap_read(regmap, ATMEL_HSMC_CYCLE(layout, cs), &conf->cycle); in atmel_hsmc_cs_conf_get()
/linux/fs/bcachefs/
H A Dbtree_locking.c182 static noinline int break_cycle(struct lock_graph *g, struct printbuf *cycle) in break_cycle() argument
192 if (cycle) { in break_cycle()
193 print_cycle(cycle, g); in break_cycle()
238 struct printbuf *cycle) in lock_graph_descend() argument
246 return break_cycle(g, cycle); in lock_graph_descend()
258 if (cycle) in lock_graph_descend()
274 int bch2_check_for_deadlock(struct btree_trans *trans, struct printbuf *cycle) in bch2_check_for_deadlock() argument
285 if (cycle) in bch2_check_for_deadlock()
296 if (cycle) in bch2_check_for_deadlock()
297 cycle->atomic++; in bch2_check_for_deadlock()
[all …]
/linux/Documentation/driver-api/thermal/
H A Dcpu-idle-cooling.rst37 decrease. Acting on the idle state duration or the idle cycle
47 At a specific OPP, we can assume that injecting idle cycle on all CPUs
61 idle state for a specified time each control cycle, it provides
71 or decreased by modulating the duty cycle of the idle injection.
86 duty cycle 25%
90 the duty cycle percentage. When no mitigation is happening the cooling
91 device state is zero, meaning the duty cycle is 0%.
95 cycle (aka the cooling device state), the running duration can be
98 The governor will change the cooling device state thus the duty cycle
114 duty cycle 33%
[all …]
/linux/drivers/net/ethernet/hisilicon/hns3/hns3pf/
H A Dhclge_ptp.c12 ptp->cycle.quo = readl(hdev->ptp->io_base + HCLGE_PTP_CYCLE_QUO_REG) & in hclge_ptp_get_cycle()
14 ptp->cycle.numer = readl(hdev->ptp->io_base + HCLGE_PTP_CYCLE_NUM_REG); in hclge_ptp_get_cycle()
15 ptp->cycle.den = readl(hdev->ptp->io_base + HCLGE_PTP_CYCLE_DEN_REG); in hclge_ptp_get_cycle()
17 if (ptp->cycle.den == 0) { in hclge_ptp_get_cycle()
28 struct hclge_ptp_cycle *cycle = &hdev->ptp->cycle; in hclge_ptp_adjfine() local
33 adj_base = (u64)cycle->quo * (u64)cycle->den + (u64)cycle->numer; in hclge_ptp_adjfine()
41 quo = div_u64_rem(adj_val, cycle->den, &numerator); in hclge_ptp_adjfine()
47 writel(cycle->den, hdev->ptp->io_base + HCLGE_PTP_CYCLE_DEN_REG); in hclge_ptp_adjfine()
/linux/drivers/net/dsa/sja1105/
H A Dsja1105_tas.c174 int cycle = 0; in sja1105_init_scheduling() local
300 schedule_entry_points[cycle].subschindx = cycle; in sja1105_init_scheduling()
301 schedule_entry_points[cycle].delta = entry_point_delta; in sja1105_init_scheduling()
302 schedule_entry_points[cycle].address = schedule_start_idx; in sja1105_init_scheduling()
307 for (i = cycle; i < 8; i++) in sja1105_init_scheduling()
319 cycle++; in sja1105_init_scheduling()
336 schedule_entry_points[cycle].subschindx = cycle; in sja1105_init_scheduling()
337 schedule_entry_points[cycle].delta = entry_point_delta; in sja1105_init_scheduling()
338 schedule_entry_points[cycle].address = schedule_start_idx; in sja1105_init_scheduling()
340 for (i = cycle; i < 8; i++) in sja1105_init_scheduling()
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dmvebu-devbus.txt40 cycle from a slow device.
53 ALE[0] to the cycle that the first read data is sampled
57 - devbus,acc-next-ps: Defines the time delay between the cycle that
58 samples data N and the cycle that samples data N+1
64 DEV_OEn and DEV_CSn are asserted at the same cycle.
73 DEV_OEn and DEV_CSn are de-asserted at the same cycle
74 (the cycle of the last data sample).
76 DEV_OEn is always de-asserted the next cycle after
85 - devbus,ale-wr-ps: Defines the time delay from the ALE[0] negation cycle

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